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Commit f4f1269c authored by Kumar Gala's avatar Kumar Gala Committed by Linus Torvalds
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[PATCH] ppc32: Remove board support for ASH 

Support for the ASH board is no longer maintained and thus being removed
Signed-off-by: default avatarKumar Gala <kumar.gala@freescale.com>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent a3800d8f
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Showing with 2 additions and 1011 deletions
arch/ppc/boot/simple/embed_config.c
View file @ f4f1269c
...@@ -784,7 +784,7 @@ embed_config(bd_t ** bdp) ...@@ -784,7 +784,7 @@ embed_config(bd_t ** bdp)
#ifdef CONFIG_IBM_OPENBIOS #ifdef CONFIG_IBM_OPENBIOS
/* This could possibly work for all treeboot roms. /* This could possibly work for all treeboot roms.
*/ */
#if defined(CONFIG_ASH) || defined(CONFIG_BEECH) || defined(CONFIG_BUBINGA) #if defined(CONFIG_BEECH) || defined(CONFIG_BUBINGA)
#define BOARD_INFO_VECTOR 0xFFF80B50 /* openbios 1.19 moved this vector down - armin */ #define BOARD_INFO_VECTOR 0xFFF80B50 /* openbios 1.19 moved this vector down - armin */
#else #else
#define BOARD_INFO_VECTOR 0xFFFE0B50 #define BOARD_INFO_VECTOR 0xFFFE0B50
......
arch/ppc/configs/ash_defconfig deleted 100644 → 0
View file @ a3800d8f
This diff is collapsed.
arch/ppc/platforms/4xx/Kconfig
View file @ f4f1269c
...@@ -16,11 +16,6 @@ choice ...@@ -16,11 +16,6 @@ choice
depends on 40x depends on 40x
default WALNUT default WALNUT
config ASH
bool "Ash"
help
This option enables support for the IBM NP405H evaluation board.
config BUBINGA config BUBINGA
bool "Bubinga" bool "Bubinga"
select WANT_EARLY_SERIAL select WANT_EARLY_SERIAL
......
arch/ppc/platforms/4xx/Makefile
View file @ f4f1269c
# #
# Makefile for the PowerPC 4xx linux kernel. # Makefile for the PowerPC 4xx linux kernel.
obj-$(CONFIG_ASH) += ash.o
obj-$(CONFIG_BAMBOO) += bamboo.o obj-$(CONFIG_BAMBOO) += bamboo.o
obj-$(CONFIG_CPCI405) += cpci405.o obj-$(CONFIG_CPCI405) += cpci405.o
obj-$(CONFIG_EBONY) += ebony.o obj-$(CONFIG_EBONY) += ebony.o
......
arch/ppc/platforms/4xx/ash.c deleted 100644 → 0
View file @ a3800d8f
/*
* arch/ppc/platforms/4xx/ash.c
*
* Support for the IBM NP405H ash eval board
*
* Author: Armin Kuster <akuster@mvista.com>
*
* 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/pagemap.h>
#include <linux/pci.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/io.h>
#include <asm/ocp.h>
#include <asm/ibm_ocp_pci.h>
#include <asm/todc.h>
#ifdef DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif
void *ash_rtc_base;
/* Some IRQs unique to Walnut.
* Used by the generic 405 PCI setup functions in ppc4xx_pci.c
*/
int __init
ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
static char pci_irq_table[][4] =
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
{24, 24, 24, 24}, /* IDSEL 1 - PCI slot 1 */
{25, 25, 25, 25}, /* IDSEL 2 - PCI slot 2 */
{26, 26, 26, 26}, /* IDSEL 3 - PCI slot 3 */
{27, 27, 27, 27}, /* IDSEL 4 - PCI slot 4 */
};
const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
return PCI_IRQ_TABLE_LOOKUP;
}
void __init
ash_setup_arch(void)
{
ppc4xx_setup_arch();
ibm_ocp_set_emac(0, 3);
#ifdef CONFIG_DEBUG_BRINGUP
int i;
printk("\n");
printk("machine\t: %s\n", PPC4xx_MACHINE_NAME);
printk("\n");
printk("bi_s_version\t %s\n", bip->bi_s_version);
printk("bi_r_version\t %s\n", bip->bi_r_version);
printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize,
bip->bi_memsize / (1024 * 1000));
for (i = 0; i < EMAC_NUMS; i++) {
printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", i,
bip->bi_enetaddr[i][0], bip->bi_enetaddr[i][1],
bip->bi_enetaddr[i][2], bip->bi_enetaddr[i][3],
bip->bi_enetaddr[i][4], bip->bi_enetaddr[i][5]);
}
printk("bi_pci_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0,
bip->bi_pci_enetaddr[0], bip->bi_pci_enetaddr[1],
bip->bi_pci_enetaddr[2], bip->bi_pci_enetaddr[3],
bip->bi_pci_enetaddr[4], bip->bi_pci_enetaddr[5]);
printk("bi_intfreq\t 0x%8.8x\t clock:\t %dMhz\n",
bip->bi_intfreq, bip->bi_intfreq / 1000000);
printk("bi_busfreq\t 0x%8.8x\t plb bus clock:\t %dMHz\n",
bip->bi_busfreq, bip->bi_busfreq / 1000000);
printk("bi_pci_busfreq\t 0x%8.8x\t pci bus clock:\t %dMHz\n",
bip->bi_pci_busfreq, bip->bi_pci_busfreq / 1000000);
printk("\n");
#endif
/* RTC step for ash */
ash_rtc_base = (void *) ASH_RTC_VADDR;
TODC_INIT(TODC_TYPE_DS1743, ash_rtc_base, ash_rtc_base, ash_rtc_base,
8);
}
void __init
bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
{
/*
* Expected PCI mapping:
*
* PLB addr PCI memory addr
* --------------------- ---------------------
* 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
* 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
*
* PLB addr PCI io addr
* --------------------- ---------------------
* e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
*
* The following code is simplified by assuming that the bootrom
* has been well behaved in following this mapping.
*/
#ifdef DEBUG
int i;
printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
printk("PCI bridge regs before fixup \n");
for (i = 0; i <= 2; i++) {
printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
printk(" pmm%dla\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
printk(" pmm%dpcila\t0x%x\n", i,
in_le32(&(pcip->pmm[i].pcila)));
printk(" pmm%dpciha\t0x%x\n", i,
in_le32(&(pcip->pmm[i].pciha)));
}
printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
early_read_config_dword(hose, hose->first_busno,
PCI_FUNC(hose->first_busno), bar,
&bar_response);
DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
hose->first_busno, PCI_SLOT(hose->first_busno),
PCI_FUNC(hose->first_busno), bar, bar_response);
}
#endif
if (ppc_md.progress)
ppc_md.progress("bios_fixup(): enter", 0x800);
/* added for IBM boot rom version 1.15 bios bar changes -AK */
/* Disable region first */
out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
/* PLB starting addr, PCI: 0x80000000 */
out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
/* PCI start addr, 0x80000000 */
out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
/* 512MB range of PLB to PCI */
out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
/* Enable no pre-fetch, enable region */
out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
(PPC405_PCI_UPPER_MEM -
PPC405_PCI_MEM_BASE)) | 0x01));
/* Disable region one */
out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
/* Disable region two */
out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
/* Enable PTM1 and PTM2, mapped to PLB address 0. */
out_le32((void *) &(pcip->ptm1la), 0x00000000);
out_le32((void *) &(pcip->ptm1ms), 0x00000001);
out_le32((void *) &(pcip->ptm2la), 0x00000000);
out_le32((void *) &(pcip->ptm2ms), 0x00000001);
/* Write zero to PTM1 BAR. */
early_write_config_dword(hose, hose->first_busno,
PCI_FUNC(hose->first_busno),
PCI_BASE_ADDRESS_1,
0x00000000);
/* Disable PTM2 (unused) */
out_le32((void *) &(pcip->ptm2la), 0x00000000);
out_le32((void *) &(pcip->ptm2ms), 0x00000000);
/* end work arround */
if (ppc_md.progress)
ppc_md.progress("bios_fixup(): done", 0x800);
#ifdef DEBUG
printk("PCI bridge regs after fixup \n");
for (i = 0; i <= 2; i++) {
printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
printk(" pmm%dla\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
printk(" pmm%dpcila\t0x%x\n", i,
in_le32(&(pcip->pmm[i].pcila)));
printk(" pmm%dpciha\t0x%x\n", i,
in_le32(&(pcip->pmm[i].pciha)));
}
printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
early_read_config_dword(hose, hose->first_busno,
PCI_FUNC(hose->first_busno), bar,
&bar_response);
DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
hose->first_busno, PCI_SLOT(hose->first_busno),
PCI_FUNC(hose->first_busno), bar, bar_response);
}
#endif
}
void __init
ash_map_io(void)
{
ppc4xx_map_io();
io_block_mapping(ASH_RTC_VADDR, ASH_RTC_PADDR, ASH_RTC_SIZE, _PAGE_IO);
}
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
ppc4xx_init(r3, r4, r5, r6, r7);
ppc_md.setup_arch = ash_setup_arch;
ppc_md.setup_io_mappings = ash_map_io;
#ifdef CONFIG_PPC_RTC
ppc_md.time_init = todc_time_init;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.get_rtc_time = todc_get_rtc_time;
ppc_md.nvram_read_val = todc_direct_read_val;
ppc_md.nvram_write_val = todc_direct_write_val;
#endif
}
arch/ppc/platforms/4xx/ash.h deleted 100644 → 0
View file @ a3800d8f
/*
* arch/ppc/platforms/4xx/ash.h
*
* Macros, definitions, and data structures specific to the IBM PowerPC
* Ash eval board.
*
* Author: Armin Kuster <akuster@mvista.com>
*
* 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifdef __KERNEL__
#ifndef __ASM_ASH_H__
#define __ASM_ASH_H__
#include <platforms/4xx/ibmnp405h.h>
#ifndef __ASSEMBLY__
/*
* Data structure defining board information maintained by the boot
* ROM on IBM's "Ash" evaluation board. An effort has been made to
* keep the field names consistent with the 8xx 'bd_t' board info
* structures.
*/
typedef struct board_info {
unsigned char bi_s_version[4]; /* Version of this structure */
unsigned char bi_r_version[30]; /* Version of the IBM ROM */
unsigned int bi_memsize; /* DRAM installed, in bytes */
unsigned char bi_enetaddr[4][6]; /* Local Ethernet MAC address */
unsigned char bi_pci_enetaddr[6];
unsigned int bi_intfreq; /* Processor speed, in Hz */
unsigned int bi_busfreq; /* PLB Bus speed, in Hz */
unsigned int bi_pci_busfreq; /* PCI speed in Hz */
} bd_t;
/* Some 4xx parts use a different timebase frequency from the internal clock.
*/
#define bi_tbfreq bi_intfreq
/* Memory map for the IBM "Ash" NP405H evaluation board.
*/
extern void *ash_rtc_base;
#define ASH_RTC_PADDR ((uint)0xf0000000)
#define ASH_RTC_VADDR ASH_RTC_PADDR
#define ASH_RTC_SIZE ((uint)8*1024)
/* Early initialization address mapping for block_io.
* Standard 405GP map.
*/
#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE)
#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR
#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR)
#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR
#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000)
#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR
#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000)
#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
#define NR_BOARD_IRQS 32
#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK
#define BASE_BAUD 201600
#else
#define BASE_BAUD 691200
#endif
#define PPC4xx_MACHINE_NAME "IBM NP405H Ash"
extern char pci_irq_table[][4];
#endif /* !__ASSEMBLY__ */
#endif /* __ASM_ASH_H__ */
#endif /* __KERNEL__ */
arch/ppc/syslib/ppc4xx_setup.c
View file @ f4f1269c
...@@ -171,7 +171,7 @@ ppc4xx_calibrate_decr(void) ...@@ -171,7 +171,7 @@ ppc4xx_calibrate_decr(void)
unsigned int freq; unsigned int freq;
bd_t *bip = &__res; bd_t *bip = &__res;
#if defined(CONFIG_WALNUT) || defined(CONFIG_ASH) || defined(CONFIG_SYCAMORE) #if defined(CONFIG_WALNUT) || defined(CONFIG_SYCAMORE)
/* Walnut boot rom sets DCR CHCR1 (aka CPC0_CR1) bit CETE to 1 */ /* Walnut boot rom sets DCR CHCR1 (aka CPC0_CR1) bit CETE to 1 */
mtdcr(DCRN_CHCR1, mfdcr(DCRN_CHCR1) & ~CHR1_CETE); mtdcr(DCRN_CHCR1, mfdcr(DCRN_CHCR1) & ~CHR1_CETE);
#endif #endif
......
include/asm-ppc/ibm4xx.h
View file @ f4f1269c
...@@ -19,10 +19,6 @@ ...@@ -19,10 +19,6 @@
#ifdef CONFIG_40x #ifdef CONFIG_40x
#if defined(CONFIG_ASH)
#include <platforms/4xx/ash.h>
#endif
#if defined(CONFIG_BUBINGA) #if defined(CONFIG_BUBINGA)
#include <platforms/4xx/bubinga.h> #include <platforms/4xx/bubinga.h>
#endif #endif
......
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