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Commit f71b3cf8 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'imx-dt64-6.10' of... 

Merge tag 'imx-dt64-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt

i.MX arm64 device tree for 6.10:

- New board support: Emcraft Systems NavQ+ Kit, Toradex Colibri iMX8DX,
  and S32G-VNP-RDB3 board.
- A series from Alexander Stein that adds empty DSI output endpoint to
  simplify DSI connection description at board level.
- Add pinmux and I2C GPIOs to support bus recovery for LX2160A.
- Add cm40 subsystem description for i.MX8 SoCs.
- A series from Frank Li that adds ADC, LPSPI and FlexSPI devices for
  imx8qm-mek board.
- Add audio devices ASRC, ESAI, SPDIF and SAI for i.MX8QXP and correct
  audio LPCG index.
- A couple of changes from Ghennadi Procopciuc that add SCMI firmware
  and uSDHC nodes for S32G SoC.
- A couple of imx8mp-msc-sm2s updates from Ian Ray improving I2C pad
  drive strength and adding SDA/SCL GPIOs for I2C devices.
- Add PCA9451A PMIC and PCF2131 RTC support for imx93-11x11-evk board.
- A series from Lucas Stach to enable HDMI display support for i.MX8MP.
- A series from Peng Fan to improve i.MX93 support for LPI2C, LPSPI, FEC
  and eQoS.
- A couple of LS1028A changes from Rob Herring to improve PCI device
  description.
- A series from Shengjiu Wang adding HDMI and PDM mic sound support for
  imx8mp-evk board.
- A number of i.MX8M Venice device improvements from Stefan Eichenberger,
  Tim Harvey and Vitor Soares.
- A series from Xu Yang that enables USB support for imx8ulp-evk and
  imx93-11x11-evk board.
- Other small and random updates on various boards.

* tag 'imx-dt64-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (78 commits)
  arm64: dts: imx93-11x11-evk: add RTC PCF2131 support
  arm64: dts: imx93-11x11-evk: add reset gpios for ethernet PHYs
  arm64: dts: imx93-11x11-evk: add sleep pinctrl for sdhc2
  arm64: dts: imx93-11x11-evk: add different usdhc pinctrl for different timing usage
  arm64: dts: imx93-11x11-evk: add sleep pinctrl for eqos and fec
  arm64: dts: imx93-11x11-evk: update resource table address
  arm64: dts: imx93: add nvmem property for eqos
  arm64: dts: imx93: add nvmem property for fec1
  arm64: dts: imx93: assign usdhc[1..3] root clock to 400MHz
  arm64: dts: imx93: add dma support for lpspi[1..8]
  arm64: dts: imx93: add dma support for lpi2c[1..8]
  arm64: dts: imx93: use FSL_EDMA_RX for rx channel
  arm64: dts: freescale: ls1028a: Add standard PCI device compatible strings to ENETC
  arm64: dts: freescale: ls1028a: Fix embedded PCI interrupt mapping
  arm64: dts: imx8qxp-mek: add cm40_i2c, wm8960 and sai[0,1,4,5]
  arm64: dts: imx8mp: Align both CSI2 pixel clock
  arm64: dts: freescale: imx8m[mp]-verdin: Update audio card name
  arm64: dts: imx8mp: Enable HDMI on TQMa8MPxL/MBa8MPxL
  arm64: dts: imx8ulp: add caam jr
  arm64: dts: imx8mp-msc-sm2s: Add i2c{1,6} sda-/scl-gpios
  ...

Link: https://lore.kernel.org/r/20240428121247.10370-4-shawnguo2@yeah.netSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 7194048c 8005c3e1
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Showing with 3022 additions and 131 deletions
arch/arm64/boot/dts/freescale/Makefile
View file @ f71b3cf8
......@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-kbox-a-230-ls.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var1.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var2.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3-ads2.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb
......@@ -98,6 +99,10 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-14-11-x.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-14-8-x.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-14-7-x.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-aster.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-eval-v3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-iris-v2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-iris.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdp-mba8xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
......@@ -166,6 +171,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb
......@@ -259,4 +265,5 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-rpidsi.dtb
dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb
dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb
dtb-$(CONFIG_ARCH_S32) += s32g399a-rdb3.dtb
dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts
View file @ f71b3cf8
......@@ -10,7 +10,7 @@
/dts-v1/;
#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include "fsl-ls1028a-kontron-sl28.dts"
#include "fsl-ls1028a-kontron-sl28-var3.dts"
/ {
model = "Kontron SMARC-sAL28 (Single PHY) on SMARC Eval 2.0 carrier";
......
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3.dts 0 → 100644
View file @ f71b3cf8
// SPDX-License-Identifier: GPL-2.0+
/*
* Device Tree file for the Kontron SMARC-sAL28 board.
*
* This is for the network variant 3 which has one ethernet ports.
*
* Copyright (C) 2024 Michael Walle <michael@walle.cc>
*
*/
/dts-v1/;
#include "fsl-ls1028a-kontron-sl28.dts"
/ {
model = "Kontron SMARC-sAL28 (Single PHY)";
compatible = "kontron,sl28-var3", "kontron,sl28", "fsl,ls1028a";
};
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View file @ f71b3cf8
......@@ -1099,21 +1099,25 @@ pcie@1f0000000 { /* Integrated Endpoint Root Complex */
0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000
/* BAR4 (PF5) - non-prefetchable memory */
0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
enetc_port0: ethernet@0,0 {
compatible = "fsl,enetc";
compatible = "pci1957,e100", "fsl,enetc";
reg = <0x000000 0 0 0 0>;
status = "disabled";
};
enetc_port1: ethernet@0,1 {
compatible = "fsl,enetc";
compatible = "pci1957,e100", "fsl,enetc";
reg = <0x000100 0 0 0 0>;
status = "disabled";
};
enetc_port2: ethernet@0,2 {
compatible = "fsl,enetc";
compatible = "pci1957,e100", "fsl,enetc";
reg = <0x000200 0 0 0 0>;
phy-mode = "internal";
status = "disabled";
......@@ -1126,14 +1130,14 @@ fixed-link {
};
enetc_mdio_pf3: mdio@0,3 {
compatible = "fsl,enetc-mdio";
compatible = "pci1957,ee01", "fsl,enetc-mdio";
reg = <0x000300 0 0 0 0>;
#address-cells = <1>;
#size-cells = <0>;
};
ethernet@0,4 {
compatible = "fsl,enetc-ptp";
compatible = "pci1957,ee02", "fsl,enetc-ptp";
reg = <0x000400 0 0 0 0>;
clocks = <&clockgen QORIQ_CLK_HWACCEL 3>;
little-endian;
......@@ -1143,7 +1147,7 @@ ethernet@0,4 {
mscc_felix: ethernet-switch@0,5 {
reg = <0x000500 0 0 0 0>;
/* IEP INT_B */
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <2>;
status = "disabled";
mscc_felix_ports: ports {
......@@ -1201,7 +1205,7 @@ fixed-link {
};
enetc_port3: ethernet@0,6 {
compatible = "fsl,enetc";
compatible = "pci1957,e100", "fsl,enetc";
reg = <0x000600 0 0 0 0>;
phy-mode = "internal";
status = "disabled";
......@@ -1216,7 +1220,7 @@ fixed-link {
rcec@1f,0 {
reg = <0x00f800 0 0 0 0>;
/* IEP INT_A */
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <1>;
};
};
......
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
View file @ f71b3cf8
......@@ -748,7 +748,10 @@ i2c0: i2c@2000000 {
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c0_scl>;
pinctrl-1 = <&i2c0_scl_gpio>;
scl-gpios = <&gpio0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
......@@ -761,6 +764,10 @@ i2c1: i2c@2010000 {
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c1_scl>;
pinctrl-1 = <&i2c1_scl_gpio>;
scl-gpios = <&gpio0 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
......@@ -773,6 +780,10 @@ i2c2: i2c@2020000 {
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c2_scl>;
pinctrl-1 = <&i2c2_scl_gpio>;
scl-gpios = <&gpio0 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
......@@ -785,6 +796,10 @@ i2c3: i2c@2030000 {
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c3_scl>;
pinctrl-1 = <&i2c3_scl_gpio>;
scl-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
......@@ -797,7 +812,10 @@ i2c4: i2c@2040000 {
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c4_scl>;
pinctrl-1 = <&i2c4_scl_gpio>;
scl-gpios = <&gpio0 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
......@@ -810,6 +828,10 @@ i2c5: i2c@2050000 {
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c5_scl>;
pinctrl-1 = <&i2c5_scl_gpio>;
scl-gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
......@@ -822,6 +844,10 @@ i2c6: i2c@2060000 {
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c6_scl>;
pinctrl-1 = <&i2c6_scl_gpio>;
scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
......@@ -834,6 +860,10 @@ i2c7: i2c@2070000 {
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c7_scl>;
pinctrl-1 = <&i2c7_scl_gpio>;
scl-gpios = <&gpio1 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
......@@ -1669,6 +1699,80 @@ pcs18: ethernet-phy@0 {
};
};
pinmux_i2crv: pinmux@70010012c {
compatible = "pinctrl-single";
reg = <0x00000007 0x0010012c 0x0 0xc>;
#address-cells = <2>;
#size-cells = <2>;
pinctrl-single,bit-per-mux;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7>;
i2c1_scl: i2c1-scl-pins {
pinctrl-single,bits = <0x0 0 0x7>;
};
i2c1_scl_gpio: i2c1-scl-gpio-pins {
pinctrl-single,bits = <0x0 0x1 0x7>;
};
i2c2_scl: i2c2-scl-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 3)>;
};
i2c2_scl_gpio: i2c2-scl-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 3) (0x7 << 3)>;
};
i2c3_scl: i2c3-scl-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 6)>;
};
i2c3_scl_gpio: i2c3-scl-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 6) (0x7 << 6)>;
};
i2c4_scl: i2c4-scl-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 9)>;
};
i2c4_scl_gpio: i2c4-scl-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 9) (0x7 << 9)>;
};
i2c5_scl: i2c5-scl-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 12)>;
};
i2c5_scl_gpio: i2c5-scl-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>;
};
i2c6_scl: i2c6-scl-pins {
pinctrl-single,bits = <0x4 0x2 0x7>;
};
i2c6_scl_gpio: i2c6-scl-gpio-pins {
pinctrl-single,bits = <0x4 0x1 0x7>;
};
i2c7_scl: i2c7-scl-pins {
pinctrl-single,bits = <0x4 0x2 0x7>;
};
i2c7_scl_gpio: i2c7-scl-gpio-pins {
pinctrl-single,bits = <0x4 0x1 0x7>;
};
i2c0_scl: i2c0-scl-pins {
pinctrl-single,bits = <0x8 0 (0x7 << 10)>;
};
i2c0_scl_gpio: i2c0-scl-gpio-pins {
pinctrl-single,bits = <0x8 (0x1 << 10) (0x7 << 10)>;
};
};
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>,
......
arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
View file @ f71b3cf8
......@@ -25,6 +25,7 @@ aliases {
i2c7 = &mpcie1_i2c;
i2c8 = &mpcie0_i2c;
i2c9 = &pcieclk_i2c;
i2c10 = &i2c5;
mmc0 = &esdhc0;
mmc1 = &esdhc1;
serial0 = &uart0;
......
arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
View file @ f71b3cf8
......@@ -71,3 +71,12 @@ variable_eeprom: eeprom@54 {
reg = <0x54>;
};
};
&i2c5 {
status = "okay";
rtc@6f {
compatible = "microchip,mcp7940x";
reg = <0x6f>;
};
};
arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi 0 → 100644
View file @ f71b3cf8
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2024 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/firmware/imx/rsrc.h>
cm40_ipg_clk: clock-cm40-ipg {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <132000000>;
clock-output-names = "cm40_ipg_clk";
};
cm40_subsys: bus@34000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x34000000 0x0 0x34000000 0x4000000>;
interrupt-parent = <&cm40_intmux>;
cm40_lpuart: serial@37220000 {
compatible = "fsl,imx8qxp-lpuart";
reg = <0x37220000 0x1000>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cm40_uart_lpcg IMX_LPCG_CLK_1>, <&cm40_uart_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
assigned-clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_M4_0_UART>;
status = "disabled";
};
cm40_i2c: i2c@37230000 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x37230000 0x1000>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cm40_i2c_lpcg IMX_LPCG_CLK_0>,
<&cm40_i2c_lpcg IMX_LPCG_CLK_4>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_M4_0_I2C>;
status = "disabled";
};
cm40_intmux: intmux@37400000 {
compatible = "fsl,imx-intmux";
reg = <0x37400000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&cm40_ipg_clk>;
clock-names = "ipg";
power-domains = <&pd IMX_SC_R_M4_0_INTMUX>;
status = "disabled";
};
cm40_uart_lpcg: clock-controller@37620000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x37620000 0x1000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>,
<&cm40_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>;
clock-output-names = "cm40_lpcg_uart_clk",
"cm40_lpcg_uart_ipg_clk";
power-domains = <&pd IMX_SC_R_M4_0_UART>;
};
cm40_i2c_lpcg: clock-controller@37630000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x37630000 0x1000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>,
<&cm40_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "cm40_lpcg_i2c_clk",
"cm40_lpcg_i2c_ipg_clk";
power-domains = <&pd IMX_SC_R_M4_0_I2C>;
};
};
arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
View file @ f71b3cf8
......@@ -21,7 +21,6 @@ jpegdec: jpegdec@58400000 {
interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
<&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
clock-names = "per", "ipg";
assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
<&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
assigned-clock-rates = <200000000>, <200000000>;
......@@ -35,7 +34,6 @@ jpegenc: jpegenc@58450000 {
interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
<&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
clock-names = "per", "ipg";
assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
<&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
assigned-clock-rates = <200000000>, <200000000>;
......
arch/arm64/boot/dts/freescale/imx8dx-colibri-aster.dts 0 → 100644
View file @ f71b3cf8
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2018-2021 Toradex
*/
/dts-v1/;
#include "imx8dx-colibri.dtsi"
#include "imx8x-colibri-aster.dtsi"
/ {
model = "Toradex Colibri iMX8DX on Aster Board";
compatible = "toradex,colibri-imx8x-aster",
"toradex,colibri-imx8x",
"fsl,imx8dx";
};
arch/arm64/boot/dts/freescale/imx8dx-colibri-eval-v3.dts 0 → 100644
View file @ f71b3cf8
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2018-2021 Toradex
*/
/dts-v1/;
#include "imx8dx-colibri.dtsi"
#include "imx8x-colibri-eval-v3.dtsi"
/ {
model = "Toradex Colibri iMX8DX on Colibri Evaluation Board V3";
compatible = "toradex,colibri-imx8x-eval-v3",
"toradex,colibri-imx8x",
"fsl,imx8dx";
};
arch/arm64/boot/dts/freescale/imx8dx-colibri-iris-v2.dts 0 → 100644
View file @ f71b3cf8
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2018-2021 Toradex
*/
/dts-v1/;
#include "imx8dx-colibri.dtsi"
#include "imx8x-colibri-iris-v2.dtsi"
/ {
model = "Toradex Colibri iMX8DX on Colibri Iris V2 Board";
compatible = "toradex,colibri-imx8x-iris-v2",
"toradex,colibri-imx8x",
"fsl,imx8dx";
};
arch/arm64/boot/dts/freescale/imx8dx-colibri-iris.dts 0 → 100644
View file @ f71b3cf8
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2018-2021 Toradex
*/
/dts-v1/;
#include "imx8dx-colibri.dtsi"
#include "imx8x-colibri-iris.dtsi"
/ {
model = "Toradex Colibri iMX8DX on Colibri Iris Board";
compatible = "toradex,colibri-imx8x-iris",
"toradex,colibri-imx8x",
"fsl,imx8dx";
};
arch/arm64/boot/dts/freescale/imx8dx-colibri.dtsi 0 → 100644
View file @ f71b3cf8
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2018-2021 Toradex
*/
#include "imx8dx.dtsi"
#include "imx8x-colibri.dtsi"
/ {
model = "Toradex Colibri iMX8DX Module";
};
arch/arm64/boot/dts/freescale/imx8dx.dtsi 0 → 100644
View file @ f71b3cf8
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2020 NXP
*/
/dts-v1/;
#include "imx8dxp.dtsi"
&gpu_3d0 {
assigned-clock-rates = <372000000>, <372000000>;
};
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
View file @ f71b3cf8
......@@ -16,6 +16,8 @@ aliases {
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &lpuart0;
serial1 = &lpuart1;
serial6 = &cm40_lpuart;
};
chosen {
......@@ -51,6 +53,16 @@ linux,cma {
};
};
m2_uart1_sel: regulator-m2uart1sel {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "m2_uart1_sel";
gpio = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
mux3_en: regulator-0 {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
......@@ -340,6 +352,12 @@ &lpuart0 {
status = "okay";
};
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
......@@ -354,6 +372,16 @@ &flexcan3 {
status = "okay";
};
&cm40_intmux {
status = "disabled";
};
&cm40_lpuart {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cm40_lpuart>;
status = "disabled";
};
&lsio_gpio4 {
status = "okay";
};
......@@ -595,6 +623,15 @@ IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020
>;
};
pinctrl_lpuart1: lpuart1grp {
fsl,pins = <
IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020
IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020
IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020
IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
......
arch/arm64/boot/dts/freescale/imx8dxl.dtsi
View file @ f71b3cf8
......@@ -5,6 +5,7 @@
#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/dma/fsl-edma.h>
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
......@@ -231,6 +232,7 @@ xtal24m: clock-xtal24m {
};
/* sorted in register address */
#include "imx8-ss-cm40.dtsi"
#include "imx8-ss-adma.dtsi"
#include "imx8-ss-conn.dtsi"
#include "imx8-ss-ddr.dtsi"
......@@ -241,3 +243,14 @@ xtal24m: clock-xtal24m {
#include "imx8dxl-ss-conn.dtsi"
#include "imx8dxl-ss-lsio.dtsi"
#include "imx8dxl-ss-ddr.dtsi"
&cm40_intmux {
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
View file @ f71b3cf8
......@@ -72,6 +72,20 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
enable-active-high;
};
reg_1v5: regulator-1v5 {
compatible = "regulator-fixed";
regulator-name = "VDD_1V5";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
};
reg_1v8: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "VDD_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_vddext_3v3: regulator-vddext-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDEXT_3V3";
......@@ -381,7 +395,7 @@ adv7535_out: endpoint {
};
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110";
compatible = "nxp,ptn5110", "tcpci";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec1>;
reg = <0x50>;
......@@ -441,6 +455,9 @@ camera@3c {
assigned-clock-rates = <24000000>;
powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
DOVDD-supply = <&buck5_reg>;
AVDD-supply = <&reg_1v8>;
DVDD-supply = <&reg_1v5>;
port {
ov5640_to_mipi_csi2: endpoint {
......
arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts
View file @ f71b3cf8
......@@ -117,7 +117,6 @@ extcon_usbotg1: typec@3d {
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ptn5150>;
status = "okay";
};
};
......
arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
View file @ f71b3cf8
......@@ -57,7 +57,7 @@ &ecspi2 {
status = "okay";
tpm@1 {
compatible = "tcg,tpm_tis-spi";
compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
reg = <0x1>;
spi-max-frequency = <36000000>;
};
......
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
View file @ f71b3cf8
......@@ -297,7 +297,7 @@ flash@0 {
};
tpm@1 {
compatible = "tcg,tpm_tis-spi";
compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
reg = <0x1>;
spi-max-frequency = <36000000>;
};
......
arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi
View file @ f71b3cf8
......@@ -10,7 +10,7 @@ sound_card: sound-card {
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "imx8mm-wm8904";
simple-audio-card,name = "verdin-wm8904";
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
......@@ -32,6 +32,25 @@ simple-audio-card,cpu {
sound-dai = <&sai2>;
};
};
reg_usb_hub: regulator-usb-hub {
compatible = "regulator-fixed";
enable-active-high;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>;
regulator-boot-on;
regulator-name = "HUB_PWR_EN";
};
reg_pcie: regulator-pcie {
compatible = "regulator-fixed";
enable-active-high;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>;
regulator-boot-on;
regulator-name = "PCIE_1_PWR_EN";
startup-delay-us = <100000>;
};
};
/* Verdin SPI_1 */
......@@ -58,6 +77,11 @@ &flexspi {
status = "okay";
};
&gpio5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
/* Current measurement into module VCC */
&hwmon {
status = "okay";
......@@ -93,6 +117,7 @@ wm8904_1a: audio-codec@1a {
/* Verdin PCIE_1 */
&pcie0 {
vpcie-supply = <&reg_pcie>;
status = "okay";
};
......@@ -115,6 +140,11 @@ &pwm3 {
status = "okay";
};
/* We support turning off sleep moci on Dahlia */
&reg_force_sleep_moci {
status = "disabled";
};
/* Verdin I2S_1 */
&sai2 {
status = "okay";
......@@ -143,8 +173,16 @@ &usbotg1 {
/* Verdin USB_2 */
&usbotg2 {
#address-cells = <1>;
#size-cells = <0>;
disable-over-current;
status = "okay";
usb-hub@1 {
compatible = "usb424,2744";
reg = <1>;
vdd-supply = <&reg_usb_hub>;
};
};
/* Verdin SD_1 */
......
arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi
View file @ f71b3cf8
......@@ -10,7 +10,7 @@ sound_card: sound-card {
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "imx8mm-nau8822";
simple-audio-card,name = "verdin-nau8822";
simple-audio-card,routing =
"Headphones", "LHP",
"Headphones", "RHP",
......@@ -78,6 +78,11 @@ &i2c3 {
status = "okay";
};
&gpio5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
&gpio_expander_21 {
status = "okay";
};
......
arch/arm64/boot/dts/freescale/imx8mm-verdin-yavia.dtsi
View file @ f71b3cf8
......@@ -81,6 +81,11 @@ &gpio3 {
pinctrl-0 = <&pinctrl_gpios_ext_yavia>;
};
&gpio5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
&hwmon_temp {
status = "okay";
};
......
arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
View file @ f71b3cf8
......@@ -110,6 +110,22 @@ reg_ethphy: regulator-ethphy {
startup-delay-us = <200000>;
};
/*
* By default we enable CTRL_SLEEP_MOCI#, this is required to have
* peripherals on the carrier board powered.
* If more granularity or power saving is required this can be disabled
* in the carrier board device tree files.
*/
reg_force_sleep_moci: regulator-force-sleep-moci {
compatible = "regulator-fixed";
enable-active-high;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>;
regulator-always-on;
regulator-boot-on;
regulator-name = "CTRL_SLEEP_MOCI#";
};
reg_usb_otg1_vbus: regulator-usb-otg1 {
compatible = "regulator-fixed";
enable-active-high;
......@@ -333,16 +349,6 @@ &gpio5 {
"SODIMM_212",
"SODIMM_151",
"SODIMM_153";
ctrl-sleep-moci-hog {
gpio-hog;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpios = <1 GPIO_ACTIVE_HIGH>;
line-name = "CTRL_SLEEP_MOCI#";
output-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
};
/* On-module I2C */
......
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View file @ f71b3cf8
......@@ -1168,6 +1168,13 @@ dsim_from_lcdif: endpoint {
remote-endpoint = <&lcdif_to_dsim>;
};
};
port@1 {
reg = <1>;
mipi_dsi_out: endpoint {
};
};
};
};
......@@ -1253,7 +1260,6 @@ usbotg1: usb@32e40000 {
reg = <0x32e40000 0x200>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
clock-names = "usb1_ctrl_root_clk";
assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
phys = <&usbphynop1>;
......@@ -1274,7 +1280,6 @@ usbotg2: usb@32e50000 {
reg = <0x32e50000 0x200>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
clock-names = "usb1_ctrl_root_clk";
assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
phys = <&usbphynop2>;
......
arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts
View file @ f71b3cf8
......@@ -112,3 +112,19 @@ ldo5: LDO5 {
};
};
};
&i2c2 {
hdmi@3d {
avdd-supply = <&buck5>;
dvdd-supply = <&buck5>;
pvdd-supply = <&buck5>;
a2vdd-supply = <&buck5>;
v1p2-supply = <&buck5>;
};
};
&i2c3 {
camera@3c {
DOVDD-supply = <&buck5>;
};
};
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
View file @ f71b3cf8
......@@ -158,3 +158,19 @@ ldo6_reg: LDO6 {
};
};
};
&i2c2 {
hdmi@3d {
avdd-supply = <&buck5_reg>;
dvdd-supply = <&buck5_reg>;
pvdd-supply = <&buck5_reg>;
a2vdd-supply = <&buck5_reg>;
v1p2-supply = <&buck5_reg>;
};
};
&i2c3 {
camera@3c {
DOVDD-supply = <&buck5_reg>;
};
};
arch/arm64/boot/dts/freescale/imx8mn-evk.dts
View file @ f71b3cf8
......@@ -125,3 +125,19 @@ ldo5: LDO5 {
};
};
};
&i2c2 {
hdmi@3d {
avdd-supply = <&buck5>;
dvdd-supply = <&buck5>;
pvdd-supply = <&buck5>;
a2vdd-supply = <&buck5>;
v1p2-supply = <&buck5>;
};
};
&i2c3 {
camera@3c {
DOVDD-supply = <&buck5>;
};
};
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
View file @ f71b3cf8
......@@ -30,7 +30,7 @@ hdmi-connector {
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&adv7533_out>;
remote-endpoint = <&adv7535_out>;
};
};
};
......@@ -52,6 +52,27 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
enable-active-high;
};
reg_1v5: regulator-1v5 {
compatible = "regulator-fixed";
regulator-name = "VDD_1V5";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
};
reg_1v8: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "VDD_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_vddext_3v3: regulator-vddext-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDEXT_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
......@@ -193,15 +214,11 @@ &i2c2 {
hdmi@3d {
compatible = "adi,adv7535";
reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>;
reg-names = "main", "cec", "edid", "packet";
reg = <0x3d>;
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
adi,dsi-lanes = <4>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
v3p3-supply = <&reg_vddext_3v3>;
ports {
#address-cells = <1>;
......@@ -210,7 +227,7 @@ ports {
port@0 {
reg = <0>;
adv7533_in: endpoint {
adv7535_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
......@@ -218,7 +235,7 @@ adv7533_in: endpoint {
port@1 {
reg = <1>;
adv7533_out: endpoint {
adv7535_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
......@@ -227,7 +244,7 @@ adv7533_out: endpoint {
};
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110";
compatible = "nxp,ptn5110", "tcpci";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec1>;
reg = <0x50>;
......@@ -284,6 +301,8 @@ camera@3c {
assigned-clock-rates = <24000000>;
powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
AVDD-supply = <&reg_1v8>;
DVDD-supply = <&reg_1v5>;
port {
ov5640_to_mipi_csi2: endpoint {
......@@ -335,7 +354,7 @@ port@1 {
reg = <1>;
dsi_out: endpoint {
remote-endpoint = <&adv7533_in>;
remote-endpoint = <&adv7535_in>;
data-lanes = <1 2 3 4>;
};
};
......
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts
View file @ f71b3cf8
......@@ -126,7 +126,6 @@ extcon_usbotg1: typec@3d {
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ptn5150>;
status = "okay";
port {
typec1_dr_sw: endpoint {
......
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View file @ f71b3cf8
......@@ -1104,6 +1104,13 @@ dsim_from_lcdif: endpoint {
remote-endpoint = <&lcdif_to_dsim>;
};
};
port@1 {
reg = <1>;
mipi_dsi_out: endpoint {
};
};
};
};
......@@ -1213,7 +1220,6 @@ usbotg1: usb@32e40000 {
reg = <0x32e40000 0x200>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
clock-names = "usb1_ctrl_root_clk";
assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
phys = <&usbphynop1>;
......
arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts
View file @ f71b3cf8
......@@ -340,7 +340,7 @@ pcieclk: clock-generator@68 {
&i2c3 {
/* Connected to USB Hub */
usb-typec@52 {
compatible = "nxp,ptn5110";
compatible = "nxp,ptn5110", "tcpci";
reg = <0x52>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
......
arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
View file @ f71b3cf8
......@@ -197,10 +197,8 @@ ldo5: LDO5 {
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
......
arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts
View file @ f71b3cf8
......@@ -144,7 +144,6 @@ &eqos {
pinctrl-0 = <&pinctrl_eqos>;
nvmem-cells = <&ethmac1>;
nvmem-cell-names = "mac-address";
phy-supply = <&reg_baseboard_vdd3v3>;
phy-handle = <&ethphy0>;
phy-mode = "rgmii-id";
status = "okay";
......
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts
View file @ f71b3cf8
......@@ -167,6 +167,16 @@ sgtl5000: codec@a {
VDDIO-supply = <&reg_vdd_3p3v_awo>;
};
csi2exp: gpio@24 {
compatible = "nxp,pca9570";
reg = <0x24>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"CSI2_#RESET", "CSI2_#PWDN",
"CSI_#PWDN", "CSI_#RESET";
};
typec@3d {
compatible = "nxp,ptn5150";
reg = <0x3d>;
......
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
View file @ f71b3cf8
......@@ -145,6 +145,27 @@ simple-audio-card,codec {
};
sound-hdmi {
compatible = "fsl,imx-audio-hdmi";
model = "audio-hdmi";
audio-cpu = <&aud2htx>;
hdmi-out;
};
sound-micfil {
compatible = "fsl,imx-audio-card";
model = "micfil-audio";
pri-dai-link {
link-name = "micfil hifi";
format = "i2s";
cpu {
sound-dai = <&micfil>;
};
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
......@@ -198,6 +219,10 @@ &A53_3 {
cpu-supply = <&reg_arm>;
};
&aud2htx {
status = "okay";
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
......@@ -524,6 +549,16 @@ &lcdif1 {
status = "okay";
};
&micfil {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pdm>;
assigned-clocks = <&clk IMX8MP_CLK_PDM>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <196608000>;
status = "okay";
};
&mipi_dsi {
samsung,esc-clock-frequency = <10000000>;
status = "okay";
......@@ -790,6 +825,16 @@ MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40
>;
};
pinctrl_pdm: pdmgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6
MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6
MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0xd6
MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0xd6
MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0xd6
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0
......
arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi
View file @ f71b3cf8
......@@ -200,8 +200,11 @@ ethphy1: ethernet-phy@1 {
};
&i2c1 {
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
clock-frequency = <400000>;
status = "okay";
......@@ -241,8 +244,11 @@ &i2c5 {
};
&i2c6 {
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c6>;
pinctrl-1 = <&pinctrl_i2c6_gpio>;
scl-gpios = <&gpio3 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio3 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
clock-frequency = <400000>;
status = "okay";
......@@ -602,38 +608,50 @@ pinctrl_flexspi0: flexspi0grp {
pinctrl_i2c1: i2c1grp {
fsl,pins =
<MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3>,
<MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3>;
<MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001e0>,
<MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001e0>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins =
<MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e0>,
<MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e0>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins =
<MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3>,
<MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3>;
<MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001e0>,
<MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001e0>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins =
<MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3>,
<MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3>;
<MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001e0>,
<MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001e0>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins =
<MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3>,
<MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3>;
<MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001e0>,
<MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001e0>;
};
pinctrl_i2c5: i2c5grp {
fsl,pins =
<MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3>,
<MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3>;
<MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001e0>,
<MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001e0>;
};
pinctrl_i2c6: i2c6grp {
fsl,pins =
<MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3>,
<MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3>;
<MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001e0>,
<MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001e0>;
};
pinctrl_i2c6_gpio: i2c6gpiogrp {
fsl,pins =
<MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x1e0>,
<MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x1e0>;
};
pinctrl_lcd0_backlight: lcd0-backlightgrp {
......
arch/arm64/boot/dts/freescale/imx8mp-navqp.dts 0 → 100644
View file @ f71b3cf8
This diff is collapsed.
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
View file @ f71b3cf8
......@@ -135,6 +135,18 @@ led-2 {
};
};
hdmi-connector {
compatible = "hdmi-connector";
label = "X44";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_out>;
};
};
};
display: display {
/*
* Display is not fixed, so compatible has to be added from
......@@ -470,6 +482,28 @@ &gpio5 {
"", "", "", "";
};
&hdmi_pvi {
status = "okay";
};
&hdmi_tx {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi>;
status = "okay";
ports {
port@1 {
hdmi_tx_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
&hdmi_tx_phy {
status = "okay";
};
&i2c2 {
clock-frequency = <384000>;
pinctrl-names = "default", "gpio";
......@@ -531,6 +565,10 @@ &i2c6 {
status = "okay";
};
&lcdif3 {
status = "okay";
};
&pcf85063 {
/* RTC_EVENT# is connected on MBa8MPxL */
pinctrl-names = "default";
......
arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi
View file @ f71b3cf8
......@@ -68,7 +68,7 @@ &ecspi2 {
status = "okay";
tpm@1 {
compatible = "tcg,tpm_tis-spi";
compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
reg = <0x1>;
spi-max-frequency = <36000000>;
};
......
arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
View file @ f71b3cf8
......@@ -8,6 +8,10 @@
#include <dt-bindings/phy/phy-imx8-pcie.h>
/ {
aliases {
ethernet1 = &eth1;
};
connector {
compatible = "gpio-usb-b-connector", "usb-b-connector";
pinctrl-names = "default";
......@@ -151,6 +155,38 @@ &pcie {
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
status = "okay";
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
pcie@3,0 {
reg = <0x1800 0 0 0 0>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
eth1: ethernet@0,0 {
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
local-mac-address = [00 00 00 00 00 00];
};
};
};
};
};
/* GPS */
......
arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
View file @ f71b3cf8
......@@ -8,6 +8,10 @@
#include <dt-bindings/phy/phy-imx8-pcie.h>
/ {
aliases {
ethernet1 = &eth1;
};
connector {
compatible = "gpio-usb-b-connector", "usb-b-connector";
pinctrl-names = "default";
......@@ -163,6 +167,38 @@ &pcie {
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
status = "okay";
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
pcie@4,0 {
reg = <0x2000 0 0 0 0>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
eth1: ethernet@0,0 {
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
local-mac-address = [00 00 00 00 00 00];
};
};
};
};
};
/* GPS */
......
arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso
View file @ f71b3cf8
......@@ -62,12 +62,25 @@ &mipi_csi_0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mipi_csi_0_in: endpoint {
remote-endpoint = <&imx219_to_mipi_csi2>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
mipi_csi_0_out: endpoint {
remote-endpoint = <&isi_in_0>;
};
};
};
};
......
arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
View file @ f71b3cf8
......@@ -404,6 +404,12 @@ channel@9c {
label = "vdd_dram";
};
channel@9e {
gw,mode = <2>;
reg = <0x9e>;
label = "vdd_1p0";
};
channel@a2 {
gw,mode = <2>;
reg = <0xa2>;
......
arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
View file @ f71b3cf8
......@@ -10,7 +10,7 @@ sound {
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "imx8mp-wm8904";
simple-audio-card,name = "verdin-wm8904";
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
......@@ -32,6 +32,25 @@ simple-audio-card,cpu {
sound-dai = <&sai1>;
};
};
reg_usb_hub: regulator-usb-hub {
compatible = "regulator-fixed";
enable-active-high;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
regulator-boot-on;
regulator-name = "HUB_PWR_EN";
};
reg_pcie: regulator-pcie {
compatible = "regulator-fixed";
enable-active-high;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
regulator-boot-on;
regulator-name = "PCIE_1_PWR_EN";
startup-delay-us = <100000>;
};
};
&backlight {
......@@ -70,6 +89,11 @@ &flexspi {
status = "okay";
};
&gpio4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
/* Current measurement into module VCC */
&hwmon {
status = "okay";
......@@ -110,8 +134,14 @@ wm8904_1a: audio-codec@1a {
};
};
/* Verdin I2C_3_HDMI */
&i2c5 {
status = "okay";
};
/* Verdin PCIE_1 */
&pcie {
vpcie-supply = <&reg_pcie>;
status = "okay";
};
......@@ -138,6 +168,11 @@ &reg_usdhc2_vmmc {
vin-supply = <&reg_3p3v>;
};
/* We support turning off sleep moci on Dahlia */
&reg_force_sleep_moci {
status = "disabled";
};
/* Verdin I2S_1 */
&sai1 {
assigned-clocks = <&clk IMX8MP_CLK_SAI1>;
......@@ -181,6 +216,25 @@ &usb3_phy1 {
status = "okay";
};
&usb_dwc3_1 {
#address-cells = <1>;
#size-cells = <0>;
usb_hub_3_0: usb-hub@1 {
compatible = "usb424,5744";
reg = <1>;
peer-hub = <&usb_hub_2_0>;
vdd-supply = <&reg_usb_hub>;
};
usb_hub_2_0: usb-hub@2 {
compatible = "usb424,2744";
reg = <2>;
peer-hub = <&usb_hub_3_0>;
vdd-supply = <&reg_usb_hub>;
};
};
/* Verdin SD_1 */
&usdhc2 {
status = "okay";
......
arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi
View file @ f71b3cf8
......@@ -22,7 +22,7 @@ sound {
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "imx8mp-nau8822";
simple-audio-card,name = "verdin-nau8822";
simple-audio-card,routing =
"Headphones", "LHP",
"Headphones", "RHP",
......@@ -93,6 +93,11 @@ &flexspi {
status = "okay";
};
&gpio4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
&gpio_expander_21 {
status = "okay";
vcc-supply = <&reg_1p8v>;
......@@ -131,6 +136,11 @@ nau8822_1a: audio-codec@1a {
};
};
/* Verdin I2C_3_HDMI */
&i2c5 {
status = "okay";
};
/* Verdin PCIE_1 */
&pcie {
status = "okay";
......
arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi
View file @ f71b3cf8
......@@ -112,6 +112,11 @@ &i2c4 {
status = "okay";
};
/* Verdin I2C_3_HDMI */
&i2c5 {
status = "okay";
};
/* Verdin PCIE_1 */
&pcie {
status = "okay";
......
arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi
View file @ f71b3cf8
......@@ -100,6 +100,11 @@ &flexcan1 {
status = "okay";
};
&gpio4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
&hwmon_temp {
status = "okay";
};
......@@ -117,6 +122,11 @@ &i2c4 {
status = "okay";
};
/* Verdin I2C_3_HDMI */
&i2c5 {
status = "okay";
};
/* Verdin PCIE_1 */
&pcie {
status = "okay";
......
arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
View file @ f71b3cf8
......@@ -116,6 +116,22 @@ reg_module_eth1phy: regulator-module-eth1phy {
vin-supply = <&reg_vdd_3v3>;
};
/*
* By default we enable CTRL_SLEEP_MOCI#, this is required to have
* peripherals on the carrier board powered.
* If more granularity or power saving is required this can be disabled
* in the carrier board device tree files.
*/
reg_force_sleep_moci: regulator-force-sleep-moci {
compatible = "regulator-fixed";
enable-active-high;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
regulator-always-on;
regulator-boot-on;
regulator-name = "CTRL_SLEEP_MOCI#";
};
reg_usb1_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
enable-active-high;
......@@ -439,16 +455,6 @@ &gpio4 {
"SODIMM_256",
"SODIMM_48",
"SODIMM_44";
ctrl-sleep-moci-hog {
gpio-hog;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpios = <29 GPIO_ACTIVE_HIGH>;
line-name = "CTRL_SLEEP_MOCI#";
output-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
};
/* On-module I2C */
......@@ -664,8 +670,6 @@ atmel_mxt_ts_mezzanine: touch-mezzanine@4a {
};
};
/* TODO: Verdin I2C_3_HDMI */
/* Verdin I2C_4_CSI */
&i2c3 {
clock-frequency = <400000>;
......@@ -764,6 +768,16 @@ eeprom_carrier_board: eeprom@57 {
};
};
/* Verdin I2C_3_HDMI */
&i2c5 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c5>;
pinctrl-1 = <&pinctrl_i2c5_gpio>;
scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
/* Verdin PCIE_1 */
&pcie {
pinctrl-names = "default";
......@@ -1106,8 +1120,6 @@ pinctrl_gpio_keys: gpiokeysgrp {
pinctrl_hdmi_hog: hdmihoggrp {
fsl,pins =
<MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019>, /* SODIMM 63 */
<MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3>, /* SODIMM 59 */
<MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3>, /* SODIMM 57 */
<MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019>; /* SODIMM 61 */
};
......@@ -1163,6 +1175,19 @@ pinctrl_i2c4_gpio: i2c4gpiogrp {
<MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c6>; /* SODIMM 12 */
};
/* Verdin I2C_3_HDMI */
pinctrl_i2c5: i2c5grp {
fsl,pins =
<MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x400001c6>, /* SODIMM 59 */
<MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x400001c6>; /* SODIMM 57 */
};
pinctrl_i2c5_gpio: i2c5gpiogrp {
fsl,pins =
<MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x400001c6>, /* SODIMM 59 */
<MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x400001c6>; /* SODIMM 57 */
};
/* Verdin I2S_2_BCLK (TOUCH_RESET#) */
pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
fsl,pins =
......
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View file @ f71b3cf8
......@@ -836,6 +836,23 @@ pgc_mediamix: power-domain@10 {
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
};
pgc_hdmimix: power-domain@14 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_HDMIMIX>;
clocks = <&clk IMX8MP_CLK_HDMI_ROOT>,
<&clk IMX8MP_CLK_HDMI_APB>;
assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>,
<&clk IMX8MP_CLK_HDMI_APB>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
<&clk IMX8MP_SYS_PLL1_133M>;
assigned-clock-rates = <500000000>, <133000000>;
};
pgc_hdmi_phy: power-domain@15 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_HDMI_PHY>;
};
pgc_mipi_phy2: power-domain@16 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
......@@ -1513,6 +1530,16 @@ micfil: audio-controller@30ca0000 {
status = "disabled";
};
aud2htx: aud2htx@30cb0000 {
compatible = "fsl,imx8mp-aud2htx";
reg = <0x30cb0000 0x10000>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG>;
clock-names = "bus";
dmas = <&sdma2 26 2 0>;
dma-names = "tx";
status = "disabled";
};
};
sdma3: dma-controller@30e00000 {
......@@ -1630,7 +1657,7 @@ mipi_csi_0: csi@32e40000 {
compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
reg = <0x32e40000 0x10000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
clock-frequency = <266000000>;
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
......@@ -1640,7 +1667,7 @@ mipi_csi_0: csi@32e40000 {
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_CLK_24M>;
assigned-clock-rates = <500000000>;
assigned-clock-rates = <266000000>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
status = "disabled";
......@@ -1725,6 +1752,13 @@ dsim_from_lcdif1: endpoint {
remote-endpoint = <&lcdif1_to_dsim>;
};
};
port@1 {
reg = <1>;
mipi_dsi_out: endpoint {
};
};
};
};
......@@ -1889,6 +1923,136 @@ hsio_blk_ctrl: blk-ctrl@32f10000 {
#power-domain-cells = <1>;
#clock-cells = <0>;
};
hdmi_blk_ctrl: blk-ctrl@32fc0000 {
compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon";
reg = <0x32fc0000 0x1000>;
clocks = <&clk IMX8MP_CLK_HDMI_APB>,
<&clk IMX8MP_CLK_HDMI_ROOT>,
<&clk IMX8MP_CLK_HDMI_REF_266M>,
<&clk IMX8MP_CLK_HDMI_24M>,
<&clk IMX8MP_CLK_HDMI_FDCC_TST>;
clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc";
power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>,
<&pgc_hdmimix>, <&pgc_hdmimix>,
<&pgc_hdmimix>, <&pgc_hdmimix>,
<&pgc_hdmimix>, <&pgc_hdmi_phy>,
<&pgc_hdmimix>, <&pgc_hdmimix>;
power-domain-names = "bus", "irqsteer", "lcdif",
"pai", "pvi", "trng",
"hdmi-tx", "hdmi-tx-phy",
"hdcp", "hrv";
#power-domain-cells = <1>;
};
irqsteer_hdmi: interrupt-controller@32fc2000 {
compatible = "fsl,imx-irqsteer";
reg = <0x32fc2000 0x1000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
fsl,channel = <1>;
fsl,num-irqs = <64>;
clocks = <&clk IMX8MP_CLK_HDMI_APB>;
clock-names = "ipg";
power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>;
};
hdmi_pvi: display-bridge@32fc4000 {
compatible = "fsl,imx8mp-hdmi-pvi";
reg = <0x32fc4000 0x1000>;
interrupt-parent = <&irqsteer_hdmi>;
interrupts = <12>;
power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
pvi_from_lcdif3: endpoint {
remote-endpoint = <&lcdif3_to_pvi>;
};
};
port@1 {
reg = <1>;
pvi_to_hdmi_tx: endpoint {
remote-endpoint = <&hdmi_tx_from_pvi>;
};
};
};
};
lcdif3: display-controller@32fc6000 {
compatible = "fsl,imx8mp-lcdif";
reg = <0x32fc6000 0x1000>;
interrupt-parent = <&irqsteer_hdmi>;
interrupts = <8>;
clocks = <&hdmi_tx_phy>,
<&clk IMX8MP_CLK_HDMI_APB>,
<&clk IMX8MP_CLK_HDMI_ROOT>;
clock-names = "pix", "axi", "disp_axi";
power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>;
status = "disabled";
port {
lcdif3_to_pvi: endpoint {
remote-endpoint = <&pvi_from_lcdif3>;
};
};
};
hdmi_tx: hdmi@32fd8000 {
compatible = "fsl,imx8mp-hdmi-tx";
reg = <0x32fd8000 0x7eff>;
interrupt-parent = <&irqsteer_hdmi>;
interrupts = <0>;
clocks = <&clk IMX8MP_CLK_HDMI_APB>,
<&clk IMX8MP_CLK_HDMI_REF_266M>,
<&clk IMX8MP_CLK_32K>,
<&hdmi_tx_phy>;
clock-names = "iahb", "isfr", "cec", "pix";
assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>;
power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
reg-io-width = <1>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi_tx_from_pvi: endpoint {
remote-endpoint = <&pvi_to_hdmi_tx>;
};
};
port@1 {
reg = <1>;
/* Point endpoint to the HDMI connector */
};
};
};
hdmi_tx_phy: phy@32fdff00 {
compatible = "fsl,imx8mp-hdmi-phy";
reg = <0x32fdff00 0x100>;
clocks = <&clk IMX8MP_CLK_HDMI_APB>,
<&clk IMX8MP_CLK_HDMI_24M>;
clock-names = "apb", "ref";
assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>;
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>;
#clock-cells = <0>;
#phy-cells = <0>;
status = "disabled";
};
};
pcie: pcie@33800000 {
......
arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts
View file @ f71b3cf8
......@@ -42,7 +42,7 @@ &i2c2 {
status = "okay";
typec_ptn5100: usb-typec@50 {
compatible = "nxp,ptn5110";
compatible = "nxp,ptn5110", "tcpci";
reg = <0x50>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
......
arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
View file @ f71b3cf8
......@@ -429,7 +429,7 @@ ldo7_reg: LDO7 {
};
typec_ptn5100: usb-typec@52 {
compatible = "nxp,ptn5110";
compatible = "nxp,ptn5110", "tcpci";
reg = <0x52>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
......
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View file @ f71b3cf8
......@@ -1290,6 +1290,13 @@ mipi_dsi_lcdif_in: endpoint@0 {
remote-endpoint = <&lcdif_mipi_dsi>;
};
};
port@1 {
reg = <1>;
mipi_dsi_out: endpoint {
};
};
};
};
......
arch/arm64/boot/dts/freescale/imx8qm-mek.dts
View file @ f71b3cf8
......@@ -39,6 +39,20 @@ reg_usdhc2_vmmc: usdhc2-vmmc {
gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
&adc0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc0>;
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
&i2c1 {
......@@ -71,6 +85,37 @@ &lpuart3 {
status = "okay";
};
&lpspi2 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>;
cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>;
status = "okay";
spidev0: spi@0 {
reg = <0>;
compatible = "rohm,dh2228fv";
spi-max-frequency = <30000000>;
};
};
&flexspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
flash0: flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <133000000>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
......@@ -130,6 +175,12 @@ IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0xc600004c
>;
};
pinctrl_adc0: adc0grp {
fsl,pins = <
IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020
......@@ -149,6 +200,41 @@ IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
>;
};
pinctrl_lpspi2: lpspi2grp {
fsl,pins = <
IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x06000040
IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x06000040
IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x06000040
>;
};
pinctrl_lpspi2_cs: lpspi2csgrp {
fsl,pins = <
IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021
IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021
>;
};
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020
......
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
View file @ f71b3cf8
......@@ -44,6 +44,22 @@ usb3_data_ss: endpoint {
};
};
};
sound-wm8960 {
compatible = "fsl,imx-audio-wm8960";
model = "wm8960-audio";
audio-cpu = <&sai1>;
audio-codec = <&wm8960>;
hp-det-gpio = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>;
audio-routing = "Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Ext Spk", "SPK_LP",
"Ext Spk", "SPK_LN",
"Ext Spk", "SPK_RP",
"Ext Spk", "SPK_RN",
"LINPUT1", "Mic Jack",
"Mic Jack", "MICB";
};
};
&dsp {
......@@ -149,7 +165,7 @@ light-sensor@44 {
};
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110";
compatible = "nxp,ptn5110", "tcpci";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
reg = <0x50>;
......@@ -188,6 +204,47 @@ typec_con_ss: endpoint {
};
&cm40_i2c {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_cm40_i2c>;
pinctrl-1 = <&pinctrl_cm40_i2c_gpio>;
scl-gpios = <&lsio_gpio1 10 GPIO_ACTIVE_HIGH>;
sda-gpios = <&lsio_gpio1 9 GPIO_ACTIVE_HIGH>;
status = "okay";
wm8960: audio-codec@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
clock-names = "mclk";
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&mclkout0_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <786432000>,
<49152000>,
<12288000>,
<12288000>;
wlf,shared-lrclk;
wlf,hp-cfg = <2 2 3>;
wlf,gpio-cfg = <1 3>;
};
pca6416: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
&cm40_intmux {
status = "okay";
};
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
......@@ -218,6 +275,53 @@ &scu_key {
status = "okay";
};
&sai0 {
#sound-dai-cells = <0>;
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&sai0_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai0>;
status = "okay";
};
&sai1 {
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&sai1_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
status = "okay";
};
&sai4 {
assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
<&sai4_lpcg IMX_LPCG_CLK_0>;
assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
fsl,sai-asynchronous;
status = "okay";
};
&sai5 {
assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
<&sai5_lpcg IMX_LPCG_CLK_0>;
assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
fsl,sai-asynchronous;
status = "okay";
};
&thermal_zones {
pmic-thermal {
polling-delay-passive = <250>;
......@@ -314,6 +418,21 @@ &vpu_core1 {
};
&iomuxc {
pinctrl_cm40_i2c: cm40i2cgrp {
fsl,pins = <
IMX8QXP_ADC_IN1_M40_I2C0_SDA 0x0600004c
IMX8QXP_ADC_IN0_M40_I2C0_SCL 0x0600004c
>;
};
pinctrl_cm40_i2c_gpio: cm40i2cgpio-grp {
fsl,pins = <
IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09 0xc600004c
IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 0xc600004c
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
......@@ -385,6 +504,25 @@ IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60
>;
};
pinctrl_sai0: sai0grp {
fsl,pins = <
IMX8QXP_SAI0_TXD_ADMA_SAI0_TXD 0x06000060
IMX8QXP_SAI0_RXD_ADMA_SAI0_RXD 0x06000040
IMX8QXP_SAI0_TXC_ADMA_SAI0_TXC 0x06000040
IMX8QXP_SAI0_TXFS_ADMA_SAI0_TXFS 0x06000040
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD 0x06000040
IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC 0x06000040
IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040
IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD 0x06000060
IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x06000040
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
......
arch/arm64/boot/dts/freescale/imx8qxp.dtsi
View file @ f71b3cf8
......@@ -317,6 +317,7 @@ map0 {
/* sorted in register address */
#include "imx8-ss-img.dtsi"
#include "imx8-ss-vpu.dtsi"
#include "imx8-ss-cm40.dtsi"
#include "imx8-ss-gpu0.dtsi"
#include "imx8-ss-adma.dtsi"
#include "imx8-ss-conn.dtsi"
......
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
View file @ f71b3cf8
......@@ -127,12 +127,70 @@ &lpi2c7 {
pinctrl-1 = <&pinctrl_lpi2c7>;
status = "okay";
ptn5150_1: typec@1d {
compatible = "nxp,ptn5150";
reg = <0x1d>;
int-gpios = <&gpiof 3 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec1>;
status = "disabled";
};
pcal6408: gpio@21 {
compatible = "nxp,pcal9554b";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
ptn5150_2: typec@3d {
compatible = "nxp,ptn5150";
reg = <0x3d>;
int-gpios = <&gpiof 5 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec2>;
status = "disabled";
};
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
over-current-active-low;
status = "okay";
};
&usbphy1 {
fsl,tx-d-cal = <110>;
status = "okay";
};
&usbmisc1 {
status = "okay";
};
&usbotg2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
over-current-active-low;
status = "okay";
};
&usbphy2 {
fsl,tx-d-cal = <110>;
status = "okay";
};
&usbmisc2 {
status = "okay";
};
&usdhc0 {
......@@ -224,6 +282,32 @@ MX8ULP_PAD_PTE13__LPI2C7_SDA 0x20
>;
};
pinctrl_typec1: typec1grp {
fsl,pins = <
MX8ULP_PAD_PTF3__PTF3 0x3
>;
};
pinctrl_typec2: typec2grp {
fsl,pins = <
MX8ULP_PAD_PTF5__PTF5 0x3
>;
};
pinctrl_usb1: usb1grp {
fsl,pins = <
MX8ULP_PAD_PTF2__USB0_ID 0x10003
MX8ULP_PAD_PTF4__USB0_OC 0x10003
>;
};
pinctrl_usb2: usb2grp {
fsl,pins = <
MX8ULP_PAD_PTD23__USB1_ID 0x10003
MX8ULP_PAD_PTF6__USB1_OC 0x10003
>;
};
pinctrl_usdhc0: usdhc0grp {
fsl,pins = <
MX8ULP_PAD_PTD1__SDHC0_CMD 0x3
......
arch/arm64/boot/dts/freescale/imx8ulp.dtsi
View file @ f71b3cf8
......@@ -252,6 +252,38 @@ pcc3: clock-controller@292d0000 {
#reset-cells = <1>;
};
crypto: crypto@292e0000 {
compatible = "fsl,sec-v4.0";
reg = <0x292e0000 0x10000>;
ranges = <0 0x292e0000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
sec_jr0: jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr@2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr2: jr@3000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x3000 0x1000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr3: jr@4000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x4000 0x1000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
};
};
tpm5: tpm@29340000 {
compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
reg = <0x29340000 0x1000>;
......@@ -472,6 +504,68 @@ usdhc2: mmc@298f0000 {
status = "disabled";
};
usbotg1: usb@29900000 {
compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
reg = <0x29900000 0x200>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_USB0>;
power-domains = <&scmi_devpd IMX8ULP_PD_USB0>;
phys = <&usbphy1>;
fsl,usbmisc = <&usbmisc1 0>;
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x8>;
rx-burst-size-dword = <0x8>;
status = "disabled";
};
usbmisc1: usbmisc@29900200 {
compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7d-usbmisc",
"fsl,imx6q-usbmisc";
reg = <0x29900200 0x200>;
#index-cells = <1>;
status = "disabled";
};
usbphy1: usb-phy@29910000 {
compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy";
reg = <0x29910000 0x10000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_USB0_PHY>;
#phy-cells = <0>;
status = "disabled";
};
usbotg2: usb@29920000 {
compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
reg = <0x29920000 0x200>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_USB1>;
power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
phys = <&usbphy2>;
fsl,usbmisc = <&usbmisc2 0>;
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x8>;
rx-burst-size-dword = <0x8>;
status = "disabled";
};
usbmisc2: usbmisc@29920200 {
compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7d-usbmisc",
"fsl,imx6q-usbmisc";
reg = <0x29920200 0x200>;
#index-cells = <1>;
status = "disabled";
};
usbphy2: usb-phy@29930000 {
compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy";
reg = <0x29930000 0x10000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_USB1_PHY>;
#phy-cells = <0>;
status = "disabled";
};
fec: ethernet@29950000 {
compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
reg = <0x29950000 0x10000>;
......
arch/arm64/boot/dts/freescale/imx93.dtsi
View file @ f71b3cf8
This diff is collapsed.
arch/arm64/boot/dts/freescale/mba8mx.dtsi
View file @ f71b3cf8
......@@ -316,17 +316,11 @@ lvds_bridge_out: endpoint {
&mipi_dsi {
samsung,burst-clock-frequency = <891000000>;
samsung,esc-clock-frequency = <20000000>;
};
ports {
port@1 {
reg = <1>;
mipi_dsi_out: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&lvds_bridge_in>;
};
};
};
&mipi_dsi_out {
data-lanes = <1 2 3 4>;
remote-endpoint = <&lvds_bridge_in>;
};
&pwm3 {
......
arch/arm64/boot/dts/freescale/s32g2.dtsi
View file @ f71b3cf8
......@@ -3,7 +3,7 @@
* NXP S32G2 SoC family
*
* Copyright (c) 2021 SUSE LLC
* Copyright (c) 2017-2021 NXP
* Copyright 2017-2021, 2024 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
......@@ -14,6 +14,18 @@ / {
#address-cells = <2>;
#size-cells = <2>;
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
scmi_buf: shm@d0000000 {
compatible = "arm,scmi-shmem";
reg = <0x0 0xd0000000 0x0 0x80>;
no-map;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
......@@ -77,6 +89,19 @@ timer {
};
firmware {
scmi {
compatible = "arm,scmi-smc";
arm,smc-id = <0xc20000fe>;
#address-cells = <1>;
#size-cells = <0>;
shmem = <&scmi_buf>;
clks: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
......@@ -113,6 +138,16 @@ uart2: serial@402bc000 {
status = "disabled";
};
usdhc0: mmc@402f0000 {
compatible = "nxp,s32g2-usdhc";
reg = <0x402f0000 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 32>, <&clks 31>, <&clks 33>;
clock-names = "ipg", "ahb", "per";
bus-width = <8>;
status = "disabled";
};
gic: interrupt-controller@50800000 {
compatible = "arm,gic-v3";
reg = <0x50800000 0x10000>,
......
arch/arm64/boot/dts/freescale/s32g274a-evb.dts
View file @ f71b3cf8
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2021 SUSE LLC
* Copyright (c) 2019-2021 NXP
* Copyright 2019-2021, 2024 NXP
*/
/dts-v1/;
......@@ -32,3 +32,7 @@ memory@80000000 {
&uart0 {
status = "okay";
};
&usdhc0 {
status = "okay";
};
arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
View file @ f71b3cf8
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2021 SUSE LLC
* Copyright (c) 2019-2021 NXP
* Copyright 2019-2021, 2024 NXP
*/
/dts-v1/;
......@@ -38,3 +38,7 @@ &uart0 {
&uart1 {
status = "okay";
};
&usdhc0 {
status = "okay";
};
arch/arm64/boot/dts/freescale/s32g3.dtsi 0 → 100644
View file @ f71b3cf8
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright 2021-2023 NXP
*
* Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
* Ciprian Costea <ciprianmarian.costea@nxp.com>
* Andra-Teodora Ilie <andra.ilie@nxp.com>
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "nxp,s32g3";
interrupt-parent = <&gic>;
#address-cells = <0x02>;
#size-cells = <0x02>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&cpu4>;
};
core1 {
cpu = <&cpu5>;
};
core2 {
cpu = <&cpu6>;
};
core3 {
cpu = <&cpu7>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
clocks = <&dfs 0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
enable-method = "psci";
clocks = <&dfs 0>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
enable-method = "psci";
clocks = <&dfs 0>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
enable-method = "psci";
clocks = <&dfs 0>;
};
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x100>;
enable-method = "psci";
clocks = <&dfs 0>;
};
cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x101>;
enable-method = "psci";
clocks = <&dfs 0>;
};
cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x102>;
enable-method = "psci";
clocks = <&dfs 0>;
};
cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x103>;
enable-method = "psci";
clocks = <&dfs 0>;
};
};
firmware {
scmi: scmi {
compatible = "arm,scmi-smc";
shmem = <&scmi_shmem>;
arm,smc-id = <0xc20000fe>;
#address-cells = <1>;
#size-cells = <0>;
dfs: protocol@13 {
reg = <0x13>;
#clock-cells = <1>;
};
clks: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
};
};
psci: psci {
compatible = "arm,psci-1.0";
method = "smc";
};
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
scmi_shmem: shm@d0000000 {
compatible = "arm,scmi-shmem";
reg = <0x0 0xd0000000 0x0 0x80>;
no-map;
};
};
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0x80000000>;
uart0: serial@401c8000 {
compatible = "nxp,s32g3-linflexuart",
"fsl,s32v234-linflexuart";
reg = <0x401c8000 0x3000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
uart1: serial@401cc000 {
compatible = "nxp,s32g3-linflexuart",
"fsl,s32v234-linflexuart";
reg = <0x401cc000 0x3000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
uart2: serial@402bc000 {
compatible = "nxp,s32g3-linflexuart",
"fsl,s32v234-linflexuart";
reg = <0x402bc000 0x3000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
usdhc0: mmc@402f0000 {
compatible = "nxp,s32g3-usdhc",
"nxp,s32g2-usdhc";
reg = <0x402f0000 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 32>,
<&clks 31>,
<&clks 33>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
gic: interrupt-controller@50800000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x50800000 0x10000>,
<0x50900000 0x200000>,
<0x50400000 0x2000>,
<0x50410000 0x2000>,
<0x50420000 0x2000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* sec-phys */
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* phys */
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* virt */
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, /* hyp-phys */
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; /* hyp-virt */
arm,no-tick-in-suspend;
};
};
arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts 0 → 100644
View file @ f71b3cf8
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright 2021-2023 NXP
*
* NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)
*/
/dts-v1/;
#include "s32g3.dtsi"
/ {
model = "NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)";
compatible = "nxp,s32g399a-rdb3", "nxp,s32g3";
aliases {
mmc0 = &usdhc0;
serial0 = &uart0;
serial1 = &uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
/* 4GiB RAM */
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0 0x80000000>,
<0x8 0x80000000 0 0x80000000>;
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&usdhc0 {
bus-width = <8>;
status = "okay";
};
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