Commit f78602ab authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 perf fixes from Ingo Molnar.

* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf/x86: disable PEBS on a guest entry.
  perf/x86: Add Intel Westmere-EX uncore support
  perf/x86: Fixes for Nehalem-EX uncore driver
  perf, x86: Fix uncore_types_exit section mismatch
parents fb344389 26a4f3c0
...@@ -1522,8 +1522,16 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr) ...@@ -1522,8 +1522,16 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL; arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask; arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask; arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
/*
* If PMU counter has PEBS enabled it is not enough to disable counter
* on a guest entry since PEBS memory write can overshoot guest entry
* and corrupt guest memory. Disabling PEBS solves the problem.
*/
arr[1].msr = MSR_IA32_PEBS_ENABLE;
arr[1].host = cpuc->pebs_enabled;
arr[1].guest = 0;
*nr = 1; *nr = 2;
return arr; return arr;
} }
......
...@@ -230,6 +230,7 @@ ...@@ -230,6 +230,7 @@
#define NHMEX_S1_MSR_MASK 0xe5a #define NHMEX_S1_MSR_MASK 0xe5a
#define NHMEX_S_PMON_MM_CFG_EN (0x1ULL << 63) #define NHMEX_S_PMON_MM_CFG_EN (0x1ULL << 63)
#define NHMEX_S_EVENT_TO_R_PROG_EV 0
/* NHM-EX Mbox */ /* NHM-EX Mbox */
#define NHMEX_M0_MSR_GLOBAL_CTL 0xca0 #define NHMEX_M0_MSR_GLOBAL_CTL 0xca0
...@@ -275,18 +276,12 @@ ...@@ -275,18 +276,12 @@
NHMEX_M_PMON_CTL_INC_SEL_MASK | \ NHMEX_M_PMON_CTL_INC_SEL_MASK | \
NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK) NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK)
#define NHMEX_M_PMON_ZDP_CTL_FVC_MASK (((1 << 11) - 1) | (1 << 23))
#define NHMEX_M_PMON_ZDP_CTL_FVC_FVID_MASK 0x1f
#define NHMEX_M_PMON_ZDP_CTL_FVC_BCMD_MASK (0x7 << 5)
#define NHMEX_M_PMON_ZDP_CTL_FVC_RSP_MASK (0x7 << 8)
#define NHMEX_M_PMON_ZDP_CTL_FVC_PBOX_INIT_ERR (1 << 23)
#define NHMEX_M_PMON_ZDP_CTL_FVC_MASK \
(NHMEX_M_PMON_ZDP_CTL_FVC_FVID_MASK | \
NHMEX_M_PMON_ZDP_CTL_FVC_BCMD_MASK | \
NHMEX_M_PMON_ZDP_CTL_FVC_RSP_MASK | \
NHMEX_M_PMON_ZDP_CTL_FVC_PBOX_INIT_ERR)
#define NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n) (0x7 << (11 + 3 * (n))) #define NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n) (0x7 << (11 + 3 * (n)))
#define WSMEX_M_PMON_ZDP_CTL_FVC_MASK (((1 << 12) - 1) | (1 << 24))
#define WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n) (0x7 << (12 + 3 * (n)))
/* /*
* use the 9~13 bits to select event If the 7th bit is not set, * use the 9~13 bits to select event If the 7th bit is not set,
* otherwise use the 19~21 bits to select event. * otherwise use the 19~21 bits to select event.
...@@ -368,6 +363,7 @@ struct intel_uncore_type { ...@@ -368,6 +363,7 @@ struct intel_uncore_type {
unsigned num_shared_regs:8; unsigned num_shared_regs:8;
unsigned single_fixed:1; unsigned single_fixed:1;
unsigned pair_ctr_ctl:1; unsigned pair_ctr_ctl:1;
unsigned *msr_offsets;
struct event_constraint unconstrainted; struct event_constraint unconstrainted;
struct event_constraint *constraints; struct event_constraint *constraints;
struct intel_uncore_pmu *pmus; struct intel_uncore_pmu *pmus;
...@@ -485,29 +481,31 @@ unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx) ...@@ -485,29 +481,31 @@ unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx)
return idx * 8 + box->pmu->type->perf_ctr; return idx * 8 + box->pmu->type->perf_ctr;
} }
static inline static inline unsigned uncore_msr_box_offset(struct intel_uncore_box *box)
unsigned uncore_msr_box_ctl(struct intel_uncore_box *box) {
struct intel_uncore_pmu *pmu = box->pmu;
return pmu->type->msr_offsets ?
pmu->type->msr_offsets[pmu->pmu_idx] :
pmu->type->msr_offset * pmu->pmu_idx;
}
static inline unsigned uncore_msr_box_ctl(struct intel_uncore_box *box)
{ {
if (!box->pmu->type->box_ctl) if (!box->pmu->type->box_ctl)
return 0; return 0;
return box->pmu->type->box_ctl + return box->pmu->type->box_ctl + uncore_msr_box_offset(box);
box->pmu->type->msr_offset * box->pmu->pmu_idx;
} }
static inline static inline unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box)
unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box)
{ {
if (!box->pmu->type->fixed_ctl) if (!box->pmu->type->fixed_ctl)
return 0; return 0;
return box->pmu->type->fixed_ctl + return box->pmu->type->fixed_ctl + uncore_msr_box_offset(box);
box->pmu->type->msr_offset * box->pmu->pmu_idx;
} }
static inline static inline unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
{ {
return box->pmu->type->fixed_ctr + return box->pmu->type->fixed_ctr + uncore_msr_box_offset(box);
box->pmu->type->msr_offset * box->pmu->pmu_idx;
} }
static inline static inline
...@@ -515,7 +513,7 @@ unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx) ...@@ -515,7 +513,7 @@ unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)
{ {
return box->pmu->type->event_ctl + return box->pmu->type->event_ctl +
(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) + (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
box->pmu->type->msr_offset * box->pmu->pmu_idx; uncore_msr_box_offset(box);
} }
static inline static inline
...@@ -523,7 +521,7 @@ unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx) ...@@ -523,7 +521,7 @@ unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)
{ {
return box->pmu->type->perf_ctr + return box->pmu->type->perf_ctr +
(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) + (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
box->pmu->type->msr_offset * box->pmu->pmu_idx; uncore_msr_box_offset(box);
} }
static inline static inline
......
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