Commit f7b81d67 authored by Stephen Boyd's avatar Stephen Boyd Committed by David S. Miller

clk: qcom: Add support for NSS/GMAC clocks and resets

Add the NSS/GMAC clocks and the TCM clock and NSS resets.
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: default avatarMathieu Olivari <mathieu@codeaurora.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent a74eab63
This diff is collapsed.
...@@ -289,5 +289,7 @@ ...@@ -289,5 +289,7 @@
#define UBI32_CORE1_CLK 279 #define UBI32_CORE1_CLK 279
#define UBI32_CORE2_CLK 280 #define UBI32_CORE2_CLK 280
#define EBI2_AON_CLK 281 #define EBI2_AON_CLK 281
#define NSSTCM_CLK_SRC 282
#define NSSTCM_CLK 283
#endif #endif
...@@ -129,4 +129,47 @@ ...@@ -129,4 +129,47 @@
#define USB30_1_PHY_RESET 112 #define USB30_1_PHY_RESET 112
#define NSSFB0_RESET 113 #define NSSFB0_RESET 113
#define NSSFB1_RESET 114 #define NSSFB1_RESET 114
#define UBI32_CORE1_CLKRST_CLAMP_RESET 115
#define UBI32_CORE1_CLAMP_RESET 116
#define UBI32_CORE1_AHB_RESET 117
#define UBI32_CORE1_AXI_RESET 118
#define UBI32_CORE2_CLKRST_CLAMP_RESET 119
#define UBI32_CORE2_CLAMP_RESET 120
#define UBI32_CORE2_AHB_RESET 121
#define UBI32_CORE2_AXI_RESET 122
#define GMAC_CORE1_RESET 123
#define GMAC_CORE2_RESET 124
#define GMAC_CORE3_RESET 125
#define GMAC_CORE4_RESET 126
#define GMAC_AHB_RESET 127
#define NSS_CH0_RST_RX_CLK_N_RESET 128
#define NSS_CH0_RST_TX_CLK_N_RESET 129
#define NSS_CH0_RST_RX_125M_N_RESET 130
#define NSS_CH0_HW_RST_RX_125M_N_RESET 131
#define NSS_CH0_RST_TX_125M_N_RESET 132
#define NSS_CH1_RST_RX_CLK_N_RESET 133
#define NSS_CH1_RST_TX_CLK_N_RESET 134
#define NSS_CH1_RST_RX_125M_N_RESET 135
#define NSS_CH1_HW_RST_RX_125M_N_RESET 136
#define NSS_CH1_RST_TX_125M_N_RESET 137
#define NSS_CH2_RST_RX_CLK_N_RESET 138
#define NSS_CH2_RST_TX_CLK_N_RESET 139
#define NSS_CH2_RST_RX_125M_N_RESET 140
#define NSS_CH2_HW_RST_RX_125M_N_RESET 141
#define NSS_CH2_RST_TX_125M_N_RESET 142
#define NSS_CH3_RST_RX_CLK_N_RESET 143
#define NSS_CH3_RST_TX_CLK_N_RESET 144
#define NSS_CH3_RST_RX_125M_N_RESET 145
#define NSS_CH3_HW_RST_RX_125M_N_RESET 146
#define NSS_CH3_RST_TX_125M_N_RESET 147
#define NSS_RST_RX_250M_125M_N_RESET 148
#define NSS_RST_TX_250M_125M_N_RESET 149
#define NSS_QSGMII_TXPI_RST_N_RESET 150
#define NSS_QSGMII_CDR_RST_N_RESET 151
#define NSS_SGMII2_CDR_RST_N_RESET 152
#define NSS_SGMII3_CDR_RST_N_RESET 153
#define NSS_CAL_PRBS_RST_N_RESET 154
#define NSS_LCKDT_RST_N_RESET 155
#define NSS_SRDS_N_RESET 156
#endif #endif
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