Commit f933b87e authored by Russell King's avatar Russell King
parents 2f27bf83 d4202806
...@@ -9,6 +9,8 @@ ...@@ -9,6 +9,8 @@
#ifndef __ASM_MACH_SYSTEM_H #ifndef __ASM_MACH_SYSTEM_H
#define __ASM_MACH_SYSTEM_H #define __ASM_MACH_SYSTEM_H
#include <mach/cputype.h>
static inline void arch_idle(void) static inline void arch_idle(void)
{ {
cpu_do_idle(); cpu_do_idle();
...@@ -16,6 +18,9 @@ static inline void arch_idle(void) ...@@ -16,6 +18,9 @@ static inline void arch_idle(void)
static inline void arch_reset(char mode, const char *cmd) static inline void arch_reset(char mode, const char *cmd)
{ {
cpu_reset(0); if (cpu_is_pxa168())
cpu_reset(0xffff0000);
else
cpu_reset(0);
} }
#endif /* __ASM_MACH_SYSTEM_H */ #endif /* __ASM_MACH_SYSTEM_H */
...@@ -312,8 +312,7 @@ static int pxa_set_target(struct cpufreq_policy *policy, ...@@ -312,8 +312,7 @@ static int pxa_set_target(struct cpufreq_policy *policy,
freqs.cpu = policy->cpu; freqs.cpu = policy->cpu;
if (freq_debug) if (freq_debug)
pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, " pr_debug("Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n",
"(SDRAM %d Mhz)\n",
freqs.new / 1000, (pxa_freq_settings[idx].div2) ? freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
(new_freq_mem / 2000) : (new_freq_mem / 1000)); (new_freq_mem / 2000) : (new_freq_mem / 1000));
......
...@@ -264,23 +264,35 @@ ...@@ -264,23 +264,35 @@
* <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
* == 0x3 for pxa300/pxa310/pxa320 * == 0x3 for pxa300/pxa310/pxa320
*/ */
#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
#define __cpu_is_pxa2xx(id) \ #define __cpu_is_pxa2xx(id) \
({ \ ({ \
unsigned int _id = (id) >> 13 & 0x7; \ unsigned int _id = (id) >> 13 & 0x7; \
_id <= 0x2; \ _id <= 0x2; \
}) })
#else
#define __cpu_is_pxa2xx(id) (0)
#endif
#ifdef CONFIG_PXA3xx
#define __cpu_is_pxa3xx(id) \ #define __cpu_is_pxa3xx(id) \
({ \ ({ \
unsigned int _id = (id) >> 13 & 0x7; \ unsigned int _id = (id) >> 13 & 0x7; \
_id == 0x3; \ _id == 0x3; \
}) })
#else
#define __cpu_is_pxa3xx(id) (0)
#endif
#if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935)
#define __cpu_is_pxa93x(id) \ #define __cpu_is_pxa93x(id) \
({ \ ({ \
unsigned int _id = (id) >> 4 & 0xfff; \ unsigned int _id = (id) >> 4 & 0xfff; \
_id == 0x683 || _id == 0x693; \ _id == 0x683 || _id == 0x693; \
}) })
#else
#define __cpu_is_pxa93x(id) (0)
#endif
#define cpu_is_pxa2xx() \ #define cpu_is_pxa2xx() \
({ \ ({ \
......
...@@ -469,9 +469,13 @@ static struct i2c_board_info __initdata palm27x_pi2c_board_info[] = { ...@@ -469,9 +469,13 @@ static struct i2c_board_info __initdata palm27x_pi2c_board_info[] = {
}, },
}; };
static struct i2c_pxa_platform_data palm27x_i2c_power_info = {
.use_pio = 1,
};
void __init palm27x_pmic_init(void) void __init palm27x_pmic_init(void)
{ {
i2c_register_board_info(1, ARRAY_AND_SIZE(palm27x_pi2c_board_info)); i2c_register_board_info(1, ARRAY_AND_SIZE(palm27x_pi2c_board_info));
pxa27x_set_i2c_power_info(NULL); pxa27x_set_i2c_power_info(&palm27x_i2c_power_info);
} }
#endif #endif
...@@ -240,6 +240,7 @@ static void __init vpac270_onenand_init(void) {} ...@@ -240,6 +240,7 @@ static void __init vpac270_onenand_init(void) {}
#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
static struct pxamci_platform_data vpac270_mci_platform_data = { static struct pxamci_platform_data vpac270_mci_platform_data = {
.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
.gpio_power = -1,
.gpio_card_detect = GPIO53_VPAC270_SD_DETECT_N, .gpio_card_detect = GPIO53_VPAC270_SD_DETECT_N,
.gpio_card_ro = GPIO52_VPAC270_SD_READONLY, .gpio_card_ro = GPIO52_VPAC270_SD_READONLY,
.detect_delay_ms = 200, .detect_delay_ms = 200,
......
...@@ -298,8 +298,8 @@ static void set_dma_control0(struct pxa168fb_info *fbi) ...@@ -298,8 +298,8 @@ static void set_dma_control0(struct pxa168fb_info *fbi)
* Set bit to enable graphics DMA. * Set bit to enable graphics DMA.
*/ */
x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0); x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0);
x |= fbi->active ? 0x00000100 : 0; x &= ~CFG_GRA_ENA_MASK;
fbi->active = 0; x |= fbi->active ? CFG_GRA_ENA(1) : CFG_GRA_ENA(0);
/* /*
* If we are in a pseudo-color mode, we need to enable * If we are in a pseudo-color mode, we need to enable
......
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