Commit f941461c authored by Rabin Vincent's avatar Rabin Vincent Committed by David S. Miller

ARM: net: bpf: fix zero right shift

The LSR instruction cannot be used to perform a zero right shift since a
0 as the immediate value (imm5) in the LSR instruction encoding means
that a shift of 32 is perfomed.  See DecodeIMMShift() in the ARM ARM.

Make the JIT skip generation of the LSR if a zero-shift is requested.

This was found using american fuzzy lop.
Signed-off-by: default avatarRabin Vincent <rabin@rab.in>
Acked-by: default avatarAlexei Starovoitov <ast@kernel.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 60aa3b08
...@@ -756,7 +756,8 @@ static int build_body(struct jit_ctx *ctx) ...@@ -756,7 +756,8 @@ static int build_body(struct jit_ctx *ctx)
case BPF_ALU | BPF_RSH | BPF_K: case BPF_ALU | BPF_RSH | BPF_K:
if (unlikely(k > 31)) if (unlikely(k > 31))
return -1; return -1;
emit(ARM_LSR_I(r_A, r_A, k), ctx); if (k)
emit(ARM_LSR_I(r_A, r_A, k), ctx);
break; break;
case BPF_ALU | BPF_RSH | BPF_X: case BPF_ALU | BPF_RSH | BPF_X:
update_on_xread(ctx); update_on_xread(ctx);
......
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