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Commit f9669187 authored by Paul Mundt's avatar Paul Mundt
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sh: Kill off the remaining ST40 cruft. 

The ST40 stuff in-tree hasn't built for some time, and hasn't been
updated for over 3 years. ST maintains their own out-of-tree changes
and rebases occasionally, and that's ultimately where all of the ST40
users go anyways.

In order for the ST40 code to be brought up to date most of the stuff
removed in this changeset would have to be rewritten anyways, so there's
very little benefit in keeping the remnants around either.
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 07782cec
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Showing with 3 additions and 672 deletions
arch/sh/drivers/pci/Makefile
View file @ f9669187
......@@ -5,7 +5,6 @@
obj-y += pci.o
obj-$(CONFIG_PCI_AUTO) += pci-auto.o
obj-$(CONFIG_CPU_SUBTYPE_ST40STB1) += pci-st40.o
obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o
obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += pci-sh7751.o ops-sh4.o
obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o
......
arch/sh/drivers/pci/pci-st40.c deleted 100644 → 0
View file @ 07782cec
This diff is collapsed.
arch/sh/drivers/pci/pci-st40.h deleted 100644 → 0
View file @ 07782cec
/*
* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* Definitions for the ST40 PCI hardware.
*/
#ifndef __PCI_ST40_H__
#define __PCI_ST40_H__
#define ST40PCI_VCR_STATUS 0x00
#define ST40PCI_VCR_VERSION 0x08
#define ST40PCI_CR 0x10
#define CR_SOFT_RESET (1<<12)
#define CR_PFCS (1<<11)
#define CR_PFE (1<<9)
#define CR_BMAM (1<<6)
#define CR_HOST (1<<5)
#define CR_CLKEN (1<<4)
#define CR_SOCS (1<<3)
#define CR_IOCS (1<<2)
#define CR_RSTCTL (1<<1)
#define CR_CFINT (1<<0)
#define CR_LOCK_MASK 0x5a000000
#define ST40PCI_LSR0 0X14
#define ST40PCI_LAR0 0x1c
#define ST40PCI_INT 0x24
#define INT_MNLTDIM (1<<15)
#define INT_TTADI (1<<14)
#define INT_TMTO (1<<9)
#define INT_MDEI (1<<8)
#define INT_APEDI (1<<7)
#define INT_SDI (1<<6)
#define INT_DPEITW (1<<5)
#define INT_PEDITR (1<<4)
#define INT_TADIM (1<<3)
#define INT_MADIM (1<<2)
#define INT_MWPDI (1<<1)
#define INT_MRDPEI (1<<0)
#define ST40PCI_INTM 0x28
#define ST40PCI_AIR 0x2c
#define ST40PCI_CIR 0x30
#define CIR_PIOTEM (1<<31)
#define CIR_RWTET (1<<26)
#define ST40PCI_AINT 0x40
#define AINT_MBI (1<<13)
#define AINT_TBTOI (1<<12)
#define AINT_MBTOI (1<<11)
#define AINT_TAI (1<<3)
#define AINT_MAI (1<<2)
#define AINT_RDPEI (1<<1)
#define AINT_WDPE (1<<0)
#define ST40PCI_AINTM 0x44
#define ST40PCI_BMIR 0x48
#define ST40PCI_PAR 0x4c
#define ST40PCI_MBR 0x50
#define ST40PCI_IOBR 0x54
#define ST40PCI_PINT 0x58
#define ST40PCI_PINTM 0x5c
#define ST40PCI_MBMR 0x70
#define ST40PCI_IOBMR 0x74
#define ST40PCI_PDR 0x78
/* H8 specific registers start here */
#define ST40PCI_WCBAR 0x7c
#define ST40PCI_LOCCFG_UNLOCK 0x34
#define ST40PCI_RBAR0 0x100
#define ST40PCI_RSR0 0x104
#define ST40PCI_RLAR0 0x108
#define ST40PCI_RBAR1 0x110
#define ST40PCI_RSR1 0x114
#define ST40PCI_RLAR1 0x118
#define ST40PCI_RBAR2 0x120
#define ST40PCI_RSR2 0x124
#define ST40PCI_RLAR2 0x128
#define ST40PCI_RBAR3 0x130
#define ST40PCI_RSR3 0x134
#define ST40PCI_RLAR3 0x138
#define ST40PCI_RBAR4 0x140
#define ST40PCI_RSR4 0x144
#define ST40PCI_RLAR4 0x148
#define ST40PCI_RBAR5 0x150
#define ST40PCI_RSR5 0x154
#define ST40PCI_RLAR5 0x158
#define ST40PCI_RBAR6 0x160
#define ST40PCI_RSR6 0x164
#define ST40PCI_RLAR6 0x168
#define ST40PCI_RBAR7 0x170
#define ST40PCI_RSR7 0x174
#define ST40PCI_RLAR7 0x178
#define ST40PCI_RBAR(n) (0x100+(0x10*(n)))
#define ST40PCI_RSR(n) (0x104+(0x10*(n)))
#define ST40PCI_RLAR(n) (0x108+(0x10*(n)))
#define ST40PCI_PERF 0x80
#define PERF_MASTER_WRITE_POSTING (1<<4)
/* H8 specific registers end here */
/* These are configs space registers */
#define ST40PCI_CSR_VID 0x10000
#define ST40PCI_CSR_DID 0x10002
#define ST40PCI_CSR_CMD 0x10004
#define ST40PCI_CSR_STATUS 0x10006
#define ST40PCI_CSR_MBAR0 0x10010
#define ST40PCI_CSR_TRDY 0x10040
#define ST40PCI_CSR_RETRY 0x10041
#define ST40PCI_CSR_MIT 0x1000d
#define ST40_IO_ADDR 0xb6000000
#endif /* __PCI_ST40_H__ */
arch/sh/kernel/cpu/sh4/probe.c
View file @ f9669187
......@@ -139,14 +139,6 @@ int __init detect_cpu_and_cache_system(void)
boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
CPU_HAS_LLSC;
break;
case 0x8000:
boot_cpu_data.type = CPU_ST40RA;
boot_cpu_data.flags |= CPU_HAS_FPU;
break;
case 0x8100:
boot_cpu_data.type = CPU_ST40GX1;
boot_cpu_data.flags |= CPU_HAS_FPU;
break;
case 0x700:
boot_cpu_data.type = CPU_SH4_501;
boot_cpu_data.icache.ways = 2;
......
arch/sh/kernel/setup.c
View file @ f9669187
......@@ -303,7 +303,6 @@ static const char *cpu_name[] = {
[CPU_SH7750S] = "SH7750S", [CPU_SH7750R] = "SH7750R",
[CPU_SH7751] = "SH7751", [CPU_SH7751R] = "SH7751R",
[CPU_SH7760] = "SH7760",
[CPU_ST40RA] = "ST40RA", [CPU_ST40GX1] = "ST40GX1",
[CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501",
[CPU_SH7770] = "SH7770", [CPU_SH7780] = "SH7780",
[CPU_SH7781] = "SH7781", [CPU_SH7343] = "SH7343",
......
arch/sh/mm/Kconfig
View file @ f9669187
......@@ -17,7 +17,7 @@ config CPU_SH4
bool
select CPU_HAS_INTEVT
select CPU_HAS_SR_RB
select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2
select CPU_HAS_PTEA if !CPU_SH4A || CPU_SHX2
select CPU_HAS_FPU if !CPU_SH4AL_DSP
config CPU_SH4A
......@@ -29,10 +29,6 @@ config CPU_SH4AL_DSP
select CPU_SH4A
select CPU_HAS_DSP
config CPU_SUBTYPE_ST40
bool
select CPU_SH4
config CPU_SHX2
bool
......@@ -152,21 +148,6 @@ config CPU_SUBTYPE_SH4_202
bool "Support SH4-202 processor"
select CPU_SH4
# ST40 Processor Support
config CPU_SUBTYPE_ST40STB1
bool "Support ST40STB1/ST40RA processors"
select CPU_SUBTYPE_ST40
help
Select ST40STB1 if you have a ST40RA CPU.
This was previously called the ST40STB1, hence the option name.
config CPU_SUBTYPE_ST40GX1
bool "Support ST40GX1 processor"
select CPU_SUBTYPE_ST40
help
Select ST40GX1 if you have a ST40GX1 CPU.
# SH-4A Processor Support
config CPU_SUBTYPE_SH7770
......
drivers/serial/sh-sci.h
View file @ f9669187
......@@ -102,12 +102,6 @@
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
# define SCIF_ONLY
#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
# define SCSPTR1 0xffe00020 /* 16 bit SCIF */
# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
# define SCIF_ONLY
#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
# include <asm/hardware.h>
# define SCIF_BASE_ADDR 0x01030000
......@@ -116,8 +110,7 @@
# define SCIF_LSR2_OFFS 0x0000024
# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,
TE=1,RE=1,REIE=1 */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
# define SCIF_ONLY
#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
......@@ -577,15 +570,6 @@ static inline int sci_rxd_in(struct uart_port *port)
return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xffe00000)
return ctrl_inw(SCSPTR1)&0x0001 ? 1 : 0; /* SCIF */
else
return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
}
#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
static inline int sci_rxd_in(struct uart_port *port)
{
......
include/asm-sh/processor.h
View file @ f9669187
......@@ -49,7 +49,7 @@ enum cpu_type {
/* SH-4 types */
CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501,
CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
/* SH-4A types */
CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3,
......
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