Commit f97b1a1d authored by Renwei Wu's avatar Renwei Wu Committed by Barry Song

ARM: dts: prima2: add resets property for VPP nodes

this patch adds missed resets property for CSR SiRFprimaII Video Post
Processor(VPP) node.
Signed-off-by: default avatarRenwei Wu <renwei.wu@csr.com>
Signed-off-by: default avatarBarry Song <Baohua.Song@csr.com>
parent 1f634d74
......@@ -137,6 +137,7 @@ vpp@90020000 {
reg = <0x90020000 0x10000>;
interrupts = <31>;
clocks = <&clks 35>;
resets = <&rstc 6>;
};
};
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment