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Commit f9936c4a authored by Sudeep Holla's avatar Sudeep Holla
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arm64: dts: juno: add information about L1 and L2 caches 

Commit a8d4636f ("arm64: cacheinfo: Remove CCSIDR-based cache
information probing") removed mechanism to extract cache information
based on CCSIDR register as the architecture explicitly states no
inference about the actual sizes of caches based on CCSIDR registers.

Commit 9a802431 ("arm64: cacheinfo: add support to override cache
levels via device tree") had already provided options to override cache
information from the device tree.

This patch adds the information about L1 and L2 caches on all variants
of Juno platform.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: default avatarSudeep Holla <sudeep.holla@arm.com>
parent 72cc1993
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arch/arm64/boot/dts/arm/juno-r1.dts
View file @ f9936c4a
...@@ -89,6 +89,12 @@ A57_0: cpu@0 { ...@@ -89,6 +89,12 @@ A57_0: cpu@0 {
reg = <0x0 0x0>; reg = <0x0 0x0>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&A57_L2>; next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>; clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
...@@ -100,6 +106,12 @@ A57_1: cpu@1 { ...@@ -100,6 +106,12 @@ A57_1: cpu@1 {
reg = <0x0 0x1>; reg = <0x0 0x1>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&A57_L2>; next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>; clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
...@@ -111,6 +123,12 @@ A53_0: cpu@100 { ...@@ -111,6 +123,12 @@ A53_0: cpu@100 {
reg = <0x0 0x100>; reg = <0x0 0x100>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>; next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>; clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
...@@ -122,6 +140,12 @@ A53_1: cpu@101 { ...@@ -122,6 +140,12 @@ A53_1: cpu@101 {
reg = <0x0 0x101>; reg = <0x0 0x101>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>; next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>; clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
...@@ -133,6 +157,12 @@ A53_2: cpu@102 { ...@@ -133,6 +157,12 @@ A53_2: cpu@102 {
reg = <0x0 0x102>; reg = <0x0 0x102>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>; next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>; clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
...@@ -144,6 +174,12 @@ A53_3: cpu@103 { ...@@ -144,6 +174,12 @@ A53_3: cpu@103 {
reg = <0x0 0x103>; reg = <0x0 0x103>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>; next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>; clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
...@@ -152,10 +188,16 @@ A53_3: cpu@103 { ...@@ -152,10 +188,16 @@ A53_3: cpu@103 {
A57_L2: l2-cache0 { A57_L2: l2-cache0 {
compatible = "cache"; compatible = "cache";
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
}; };
A53_L2: l2-cache1 { A53_L2: l2-cache1 {
compatible = "cache"; compatible = "cache";
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
}; };
}; };
......
arch/arm64/boot/dts/arm/juno-r2.dts
View file @ f9936c4a
...@@ -89,6 +89,12 @@ A72_0: cpu@0 { ...@@ -89,6 +89,12 @@ A72_0: cpu@0 {
reg = <0x0 0x0>; reg = <0x0 0x0>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&A72_L2>; next-level-cache = <&A72_L2>;
clocks = <&scpi_dvfs 0>; clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
...@@ -100,6 +106,12 @@ A72_1: cpu@1 { ...@@ -100,6 +106,12 @@ A72_1: cpu@1 {
reg = <0x0 0x1>; reg = <0x0 0x1>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&A72_L2>; next-level-cache = <&A72_L2>;
clocks = <&scpi_dvfs 0>; clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
...@@ -111,6 +123,12 @@ A53_0: cpu@100 { ...@@ -111,6 +123,12 @@ A53_0: cpu@100 {
reg = <0x0 0x100>; reg = <0x0 0x100>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>; next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>; clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
...@@ -122,6 +140,12 @@ A53_1: cpu@101 { ...@@ -122,6 +140,12 @@ A53_1: cpu@101 {
reg = <0x0 0x101>; reg = <0x0 0x101>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>; next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>; clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
...@@ -133,6 +157,12 @@ A53_2: cpu@102 { ...@@ -133,6 +157,12 @@ A53_2: cpu@102 {
reg = <0x0 0x102>; reg = <0x0 0x102>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>; next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>; clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
...@@ -144,6 +174,12 @@ A53_3: cpu@103 { ...@@ -144,6 +174,12 @@ A53_3: cpu@103 {
reg = <0x0 0x103>; reg = <0x0 0x103>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>; next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>; clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
...@@ -152,10 +188,16 @@ A53_3: cpu@103 { ...@@ -152,10 +188,16 @@ A53_3: cpu@103 {
A72_L2: l2-cache0 { A72_L2: l2-cache0 {
compatible = "cache"; compatible = "cache";
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
}; };
A53_L2: l2-cache1 { A53_L2: l2-cache1 {
compatible = "cache"; compatible = "cache";
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
}; };
}; };
......
arch/arm64/boot/dts/arm/juno.dts
View file @ f9936c4a
...@@ -88,6 +88,12 @@ A57_0: cpu@0 { ...@@ -88,6 +88,12 @@ A57_0: cpu@0 {
reg = <0x0 0x0>; reg = <0x0 0x0>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&A57_L2>; next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>; clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
...@@ -99,6 +105,12 @@ A57_1: cpu@1 { ...@@ -99,6 +105,12 @@ A57_1: cpu@1 {
reg = <0x0 0x1>; reg = <0x0 0x1>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&A57_L2>; next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>; clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
...@@ -110,6 +122,12 @@ A53_0: cpu@100 { ...@@ -110,6 +122,12 @@ A53_0: cpu@100 {
reg = <0x0 0x100>; reg = <0x0 0x100>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>; next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>; clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
...@@ -121,6 +139,12 @@ A53_1: cpu@101 { ...@@ -121,6 +139,12 @@ A53_1: cpu@101 {
reg = <0x0 0x101>; reg = <0x0 0x101>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>; next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>; clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
...@@ -132,6 +156,12 @@ A53_2: cpu@102 { ...@@ -132,6 +156,12 @@ A53_2: cpu@102 {
reg = <0x0 0x102>; reg = <0x0 0x102>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>; next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>; clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
...@@ -143,6 +173,12 @@ A53_3: cpu@103 { ...@@ -143,6 +173,12 @@ A53_3: cpu@103 {
reg = <0x0 0x103>; reg = <0x0 0x103>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>; next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>; clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
...@@ -151,10 +187,16 @@ A53_3: cpu@103 { ...@@ -151,10 +187,16 @@ A53_3: cpu@103 {
A57_L2: l2-cache0 { A57_L2: l2-cache0 {
compatible = "cache"; compatible = "cache";
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
}; };
A53_L2: l2-cache1 { A53_L2: l2-cache1 {
compatible = "cache"; compatible = "cache";
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
}; };
}; };
......
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