Commit f9dc51cc authored by Mark Brown's avatar Mark Brown

Merge series "Do not handle MCLK device clock in simple-card-utils" from...

Merge series "Do not handle MCLK device clock in simple-card-utils" from Sameer Pujar <spujar@nvidia.com>:

With commit 1e30f642 ("ASoC: simple-card-utils: Fix device module clock")
simple-card-utils can control MCLK clock for rate updates or enable/disable.
But this is breaking some platforms where it is expected that codec drivers
would actually handle the MCLK clock. One such example is following platform.
  - "arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts"

In above case codec, wm8904, is using internal PLL and configures sysclk
based on fixed MCLK input. In such cases it is expected that, required PLL
output or sysclk, is just passed via set_sysclk() callback and card driver
need not actually update MCLK rate. Instead, codec can take ownership of
this clock and do the necessary configuration.

So the original commit is reverted and codec driver for rt5659 is updated
to fix my board which has this codec.

Sameer Pujar (2):
  ASoC: simple-card-utils: Do not handle device clock
  ASoC: rt5659: Update MCLK rate in set_sysclk()

 sound/soc/codecs/rt5659.c             |  5 +++++
 sound/soc/generic/simple-card-utils.c | 13 +++++++------
 2 files changed, 12 insertions(+), 6 deletions(-)

--
2.7.4
parents 9deef665 dbf54a95
...@@ -3426,12 +3426,17 @@ static int rt5659_set_component_sysclk(struct snd_soc_component *component, int ...@@ -3426,12 +3426,17 @@ static int rt5659_set_component_sysclk(struct snd_soc_component *component, int
{ {
struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component); struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0; unsigned int reg_val = 0;
int ret;
if (freq == rt5659->sysclk && clk_id == rt5659->sysclk_src) if (freq == rt5659->sysclk && clk_id == rt5659->sysclk_src)
return 0; return 0;
switch (clk_id) { switch (clk_id) {
case RT5659_SCLK_S_MCLK: case RT5659_SCLK_S_MCLK:
ret = clk_set_rate(rt5659->mclk, freq);
if (ret)
return ret;
reg_val |= RT5659_SCLK_SRC_MCLK; reg_val |= RT5659_SCLK_SRC_MCLK;
break; break;
case RT5659_SCLK_S_PLL1: case RT5659_SCLK_S_PLL1:
......
...@@ -172,15 +172,16 @@ int asoc_simple_parse_clk(struct device *dev, ...@@ -172,15 +172,16 @@ int asoc_simple_parse_clk(struct device *dev,
* or device's module clock. * or device's module clock.
*/ */
clk = devm_get_clk_from_child(dev, node, NULL); clk = devm_get_clk_from_child(dev, node, NULL);
if (IS_ERR(clk))
clk = devm_get_clk_from_child(dev, dlc->of_node, NULL);
if (!IS_ERR(clk)) { if (!IS_ERR(clk)) {
simple_dai->clk = clk;
simple_dai->sysclk = clk_get_rate(clk); simple_dai->sysclk = clk_get_rate(clk);
} else if (!of_property_read_u32(node, "system-clock-frequency",
&val)) { simple_dai->clk = clk;
} else if (!of_property_read_u32(node, "system-clock-frequency", &val)) {
simple_dai->sysclk = val; simple_dai->sysclk = val;
} else {
clk = devm_get_clk_from_child(dev, dlc->of_node, NULL);
if (!IS_ERR(clk))
simple_dai->sysclk = clk_get_rate(clk);
} }
if (of_property_read_bool(node, "system-clock-direction-out")) if (of_property_read_bool(node, "system-clock-direction-out"))
......
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