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Commit f9e224eb authored by David S. Miller's avatar David S. Miller
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Merge nuts.ninka.net:/home/davem/src/BK/cheetahplus-2.5 

into nuts.ninka.net:/home/davem/src/BK/sparc-2.5
parents 107b218e 5aada120
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Showing with 154 additions and 197 deletions
arch/sparc64/kernel/cpu.c
View file @ f9e224eb
......@@ -57,25 +57,24 @@ unsigned int fsr_storage;
void __init cpu_probe(void)
{
int manuf, impl;
unsigned i, cpuid;
long ver, fpu_vers;
long fprs;
unsigned long ver, fpu_vers, manuf, impl, fprs;
int i, cpuid;
cpuid = hard_smp_processor_id();
fprs = fprs_read ();
fprs_write (FPRS_FEF);
fprs = fprs_read();
fprs_write(FPRS_FEF);
__asm__ __volatile__ ("rdpr %%ver, %0; stx %%fsr, [%1]"
: "=&r" (ver)
: "r" (&fpu_vers));
fprs_write (fprs);
fprs_write(fprs);
manuf = ((ver >> 48) & 0xffff);
impl = ((ver >> 32) & 0xffff);
fpu_vers = ((fpu_vers >> 17) & 0x7);
retry:
for (i = 0; i < NSPARCCHIPS; i++) {
if (linux_sparc_chips[i].manuf == manuf) {
if (linux_sparc_chips[i].impl == impl) {
......@@ -87,8 +86,17 @@ void __init cpu_probe(void)
}
if (i == NSPARCCHIPS) {
printk("DEBUG: manuf = 0x%x impl = 0x%x\n",
manuf, impl);
/* Maybe it is a cheetah+ derivative, report it as cheetah+
* in that case until we learn the real names.
*/
if (manuf == 0x3e &&
impl > 0x15) {
impl = 0x15;
goto retry;
} else {
printk("DEBUG: manuf[%lx] impl[%lx]\n",
manuf, impl);
}
sparc_cpu_type[cpuid] = "Unknown CPU";
}
......@@ -104,9 +112,8 @@ void __init cpu_probe(void)
}
if (i == NSPARCFPU) {
printk("DEBUG: manuf = 0x%x impl = 0x%x fsr.vers = 0x%x\n",
manuf, impl,
(unsigned int) fpu_vers);
printk("DEBUG: manuf[%lx] impl[%lx] fsr.vers[%lx]\n",
manuf, impl, fpu_vers);
sparc_fpu_type[cpuid] = "Unknown FPU";
}
}
arch/sparc64/kernel/entry.S
View file @ f9e224eb
......@@ -1820,23 +1820,13 @@ do_gettimeofday: /* %o0 = timevalp */
ldx [%g3 + %lo(timer_tick_offset)], %g3
or %g2, %lo(xtime), %g2
or %g1, %lo(timer_tick_compare), %g1
1: rdpr %ver, %o2
sethi %hi(CHEETAH_ID), %o1
srlx %o2, 32, %o2
or %o1, %lo(CHEETAH_ID), %o1
membar #Sync
1: membar #Sync
ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %o4
cmp %o2, %o1
be,a,pn %xcc, 3f
rd %asr24, %o1
sethi %hi(CHEETAH_PLUS_ID), %o1
or %o1, %lo(CHEETAH_PLUS_ID), %o1
cmp %o2, %o1
bne,pt %xcc, 2f
nop
BRANCH_IF_ANY_CHEETAH(o2,o1,2f)
ba,pt %xcc, 3f
rd %tick, %o1
2: ba,pt %xcc, 3f
rd %asr24, %o1
2: rd %tick, %o1
3: ldx [%g1], %g7
membar #Sync
ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %o2
......
arch/sparc64/kernel/etrap.S
View file @ f9e224eb
......@@ -115,11 +115,12 @@ etraptl1: /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself.
* 0x00 TL1's TSTATE
* 0x08 TL1's TPC
* 0x10 TL1's TNPC
* 0x18 TL1's TT
* ...
* 0x58 TL4's TNPC
* 0x58 TL4's TT
* 0x60 TL
*/
sub %sp, (24 * 8) + 8, %g2
sub %sp, ((4 * 8) * 4) + 8, %g2
rdpr %tl, %g1
wrpr %g0, 1, %tl
......@@ -129,33 +130,41 @@ etraptl1: /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself.
stx %g3, [%g2 + STACK_BIAS + 0x08]
rdpr %tnpc, %g3
stx %g3, [%g2 + STACK_BIAS + 0x10]
rdpr %tt, %g3
stx %g3, [%g2 + STACK_BIAS + 0x18]
wrpr %g0, 2, %tl
rdpr %tstate, %g3
stx %g3, [%g2 + STACK_BIAS + 0x18]
rdpr %tpc, %g3
stx %g3, [%g2 + STACK_BIAS + 0x20]
rdpr %tnpc, %g3
rdpr %tpc, %g3
stx %g3, [%g2 + STACK_BIAS + 0x28]
rdpr %tnpc, %g3
stx %g3, [%g2 + STACK_BIAS + 0x30]
rdpr %tt, %g3
stx %g3, [%g2 + STACK_BIAS + 0x38]
wrpr %g0, 3, %tl
rdpr %tstate, %g3
stx %g3, [%g2 + STACK_BIAS + 0x30]
stx %g3, [%g2 + STACK_BIAS + 0x40]
rdpr %tpc, %g3
stx %g3, [%g2 + STACK_BIAS + 0x38]
stx %g3, [%g2 + STACK_BIAS + 0x48]
rdpr %tnpc, %g3
stx %g3, [%g2 + STACK_BIAS + 0x40]
stx %g3, [%g2 + STACK_BIAS + 0x50]
rdpr %tt, %g3
stx %g3, [%g2 + STACK_BIAS + 0x58]
wrpr %g0, 4, %tl
rdpr %tstate, %g3
stx %g3, [%g2 + STACK_BIAS + 0x48]
stx %g3, [%g2 + STACK_BIAS + 0x60]
rdpr %tpc, %g3
stx %g3, [%g2 + STACK_BIAS + 0x50]
stx %g3, [%g2 + STACK_BIAS + 0x68]
rdpr %tnpc, %g3
stx %g3, [%g2 + STACK_BIAS + 0x58]
stx %g3, [%g2 + STACK_BIAS + 0x70]
rdpr %tt, %g3
stx %g3, [%g2 + STACK_BIAS + 0x78]
wrpr %g1, %tl
stx %g1, [%g2 + STACK_BIAS + 0x60]
stx %g1, [%g2 + STACK_BIAS + 0x80]
rdpr %tstate, %g1 ! Single Group+4bubbles
sub %g2, REGWIN_SZ + TRACEREG_SZ - STACK_BIAS, %g2 ! IEU1
......
arch/sparc64/kernel/head.S
View file @ f9e224eb
......@@ -78,16 +78,9 @@ sparc_ramdisk_size:
* PROM entry point is on %o4
*/
sparc64_boot:
rdpr %ver, %g1
sethi %hi(CHEETAH_ID), %g5
srlx %g1, 32, %g1
or %g5, %lo(CHEETAH_ID), %g5
cmp %g1, %g5
be,pn %icc, cheetah_boot
sethi %hi(CHEETAH_PLUS_ID), %g5
or %g5, %lo(CHEETAH_PLUS_ID), %g5
cmp %g1, %g5
bne,pt %icc, spitfire_boot
BRANCH_IF_CHEETAH_BASE(g1,g5,cheetah_boot)
BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g5,cheetah_plus_boot)
ba,pt %xcc, spitfire_boot
nop
cheetah_plus_boot:
......@@ -212,15 +205,11 @@ cheetah_got_tlbentry:
add %l0, (1 << 3), %l0
/* On Cheetah+, have to check second DTLB. */
rdpr %ver, %g1
srlx %g1, 32, %g1
sethi %hi(CHEETAH_PLUS_ID), %l0
or %l0, %lo(CHEETAH_PLUS_ID), %l0
cmp %g1, %l0
bne,pt %icc, 9f
BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,l0,2f)
ba,pt %xcc, 9f
nop
set 3 << 16, %l0
2: set 3 << 16, %l0
1: ldxa [%l0] ASI_DTLB_TAG_READ, %g1
membar #Sync
andn %g1, %l2, %g1
......@@ -469,16 +458,9 @@ sun4u_init:
stxa %g3, [%g2] ASI_DMMU
membar #Sync
rdpr %ver, %g1
sethi %hi(CHEETAH_ID), %g5
srlx %g1, 32, %g1
or %g5, %lo(CHEETAH_ID), %g5
cmp %g1, %g5
be,pn %icc, cheetah_tlb_fixup
sethi %hi(CHEETAH_PLUS_ID), %g5
or %g5, %lo(CHEETAH_PLUS_ID), %g5
cmp %g1, %g5
bne,pt %icc, spitfire_tlb_fixup
BRANCH_IF_ANY_CHEETAH(g1,g5,cheetah_tlb_fixup)
ba,pt %xcc, spitfire_tlb_fixup
nop
cheetah_tlb_fixup:
......@@ -499,15 +481,10 @@ cheetah_tlb_fixup:
flush %g3
membar #Sync
sethi %hi(CHEETAH_PLUS_ID), %g5
or %g5, %lo(CHEETAH_PLUS_ID), %g5
rdpr %ver, %g2
srlx %g2, 32, %g2
cmp %g2, %g5
bne,a,pt %icc, 1f
mov 1, %g2 /* Set TLB type to cheetah. */
mov 2, %g2 /* Set TLB type to cheetah+. */
BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g5,g2,1f)
mov 1, %g2 /* Set TLB type to cheetah. */
1: sethi %hi(tlb_type), %g5
stw %g2, [%g5 + %lo(tlb_type)]
......@@ -631,16 +608,8 @@ setup_tba: /* i0 = is_starfire */
sllx %g2, 32, %g2
or %g2, KERN_LOWBITS, %g2
rdpr %ver, %g3
sethi %hi(CHEETAH_ID), %g7
srlx %g3, 32, %g3
or %g7, %lo(CHEETAH_ID), %g7
cmp %g3, %g7
be,pn %icc, cheetah_vpte_base
sethi %hi(CHEETAH_PLUS_ID), %g7
or %g7, %lo(CHEETAH_PLUS_ID), %g7
cmp %g3, %g7
bne,pt %icc, spitfire_vpte_base
BRANCH_IF_ANY_CHEETAH(g3,g7,cheetah_vpte_base)
ba,pt %xcc, spitfire_vpte_base
nop
cheetah_vpte_base:
......@@ -648,6 +617,7 @@ cheetah_vpte_base:
or %g3, %ulo(VPTE_BASE_CHEETAH), %g3
ba,pt %xcc, 2f
sllx %g3, 32, %g3
spitfire_vpte_base:
sethi %uhi(VPTE_BASE_SPITFIRE), %g3
or %g3, %ulo(VPTE_BASE_SPITFIRE), %g3
......@@ -675,16 +645,9 @@ spitfire_vpte_base:
nop
not_starfire:
rdpr %ver, %g1
sethi %hi(CHEETAH_ID), %g5
srlx %g1, 32, %g1
or %g5, %lo(CHEETAH_ID), %g5
cmp %g1, %g5
be,pn %icc, is_cheetah
sethi %hi(CHEETAH_PLUS_ID), %g5
or %g5, %lo(CHEETAH_PLUS_ID), %g5
cmp %g1, %g5
bne,pt %icc, not_cheetah
BRANCH_IF_ANY_CHEETAH(g1,g5,is_cheetah)
ba,pt %xcc, not_cheetah
nop
is_cheetah:
......@@ -710,23 +673,16 @@ set_worklist:
/* Kill PROM timer */
wr %g0, 0, %tick_cmpr
rdpr %ver, %g1
sethi %hi(CHEETAH_ID), %g5
srlx %g1, 32, %g1
or %g5, %lo(CHEETAH_ID), %g5
cmp %g1, %g5
be,pn %icc, 1f
sethi %hi(CHEETAH_PLUS_ID), %g5
or %g5, %lo(CHEETAH_PLUS_ID), %g5
cmp %g1, %g5
bne,pt %icc, 2f
BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
ba,pt %xcc, 2f
nop
/* Disable STICK_INT interrupts. */
1:
sethi %hi(0x80000000), %g1
sllx %g1, 32, %g1
wr %g1, %asr25
sethi %hi(0x80000000), %g1
sllx %g1, 32, %g1
wr %g1, %asr25
/* Ok, we're done setting up all the state our trap mechanims needs,
* now get back into normal globals and let the PROM know what is up.
......
arch/sparc64/kernel/trampoline.S
View file @ f9e224eb
......@@ -33,16 +33,10 @@ dtlb_load:
sparc64_cpu_startup:
flushw
rdpr %ver, %g1
sethi %hi(CHEETAH_ID), %g5
srlx %g1, 32, %g1
or %g5, %lo(CHEETAH_ID), %g5
cmp %g1, %g5
be,pn %icc, cheetah_startup
sethi %hi(CHEETAH_PLUS_ID), %g5
or %g5, %lo(CHEETAH_PLUS_ID), %g5
cmp %g1, %g5
bne,pt %icc, spitfire_startup
BRANCH_IF_CHEETAH_BASE(g1,g5,cheetah_startup)
BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g5,cheetah_plus_startup)
ba,pt %xcc, spitfire_startup
nop
cheetah_plus_startup:
......@@ -51,15 +45,15 @@ cheetah_plus_startup:
nop
cheetah_startup:
mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
wr %g1, %asr18
sethi %uhi(DCU_ME | DCU_RE | /*DCU_PE |*/ DCU_HPE | DCU_SPE | DCU_SL | DCU_WE), %g5
or %g5, %ulo(DCU_ME | DCU_RE | /*DCU_PE |*/ DCU_HPE | DCU_SPE | DCU_SL | DCU_WE), %g5
sllx %g5, 32, %g5
or %g5, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g5
stxa %g5, [%g0] ASI_DCU_CONTROL_REG
membar #Sync
mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
wr %g1, %asr18
sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
or %g5, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
sllx %g5, 32, %g5
or %g5, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g5
stxa %g5, [%g0] ASI_DCU_CONTROL_REG
membar #Sync
cheetah_generic_startup:
mov TSB_EXTENSION_P, %g3
......@@ -127,19 +121,10 @@ startup_continue:
ldx [%g2 + %lo(kern_locked_tte_data)], %g2
stx %g2, [%sp + 2047 + 128 + 0x30]
rdpr %ver, %g1
sethi %hi(CHEETAH_ID), %g5
srlx %g1, 32, %g1
or %g5, %lo(CHEETAH_ID), %g5
cmp %g1, %g5
be,a,pn %icc, 1f
mov 15, %g2
sethi %hi(CHEETAH_PLUS_ID), %g5
or %g5, %lo(CHEETAH_PLUS_ID), %g5
cmp %g1, %g5
bne,a,pt %icc, 1f
mov 63, %g2
mov 15, %g2
BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
mov 63, %g2
1:
stx %g2, [%sp + 2047 + 128 + 0x38]
sethi %hi(p1275buf), %g2
......@@ -167,19 +152,10 @@ startup_continue:
ldx [%g2 + %lo(kern_locked_tte_data)], %g2
stx %g2, [%sp + 2047 + 128 + 0x30]
rdpr %ver, %g1
sethi %hi(CHEETAH_ID), %g5
srlx %g1, 32, %g1
or %g5, %lo(CHEETAH_ID), %g5
cmp %g1, %g5
be,a,pn %icc, 1f
mov 15, %g2
sethi %hi(CHEETAH_PLUS_ID), %g5
or %g5, %lo(CHEETAH_PLUS_ID), %g5
cmp %g1, %g5
bne,a,pt %icc, 1f
mov 63, %g2
mov 15, %g2
BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
mov 63, %g2
1:
stx %g2, [%sp + 2047 + 128 + 0x38]
......@@ -244,16 +220,9 @@ startup_continue:
sllx %g2, 32, %g2
or %g2, KERN_LOWBITS, %g2
rdpr %ver, %g3
sethi %hi(CHEETAH_ID), %g7
srlx %g3, 32, %g3
or %g7, %lo(CHEETAH_ID), %g7
cmp %g3, %g7
be,pn %icc, 9f
sethi %hi(CHEETAH_PLUS_ID), %g7
or %g7, %lo(CHEETAH_PLUS_ID), %g7
cmp %g3, %g7
bne,pt %icc, 1f
BRANCH_IF_ANY_CHEETAH(g3,g7,9f)
ba,pt %xcc, 1f
nop
9:
......
arch/sparc64/kernel/traps.c
View file @ f9e224eb
......@@ -47,6 +47,7 @@ struct tl1_traplog {
unsigned long tstate;
unsigned long tpc;
unsigned long tnpc;
unsigned long tt;
} trapstack[4];
unsigned long tl;
};
......@@ -58,9 +59,12 @@ static void dump_tl1_traplog(struct tl1_traplog *p)
printk("TRAPLOG: Error at trap level 0x%lx, dumping track stack.\n",
p->tl);
for (i = 0; i < 4; i++) {
printk("TRAPLOG: Trap level %d TSTATE[%016lx] TPC[%016lx] TNPC[%016lx]\n",
printk(KERN_CRIT
"TRAPLOG: Trap level %d TSTATE[%016lx] TPC[%016lx] "
"TNPC[%016lx] TT[%lx]\n",
i + 1,
p->trapstack[i].tstate, p->trapstack[i].tpc, p->trapstack[i].tnpc);
p->trapstack[i].tstate, p->trapstack[i].tpc,
p->trapstack[i].tnpc, p->trapstack[i].tt);
}
}
......@@ -182,43 +186,36 @@ extern volatile int pci_poke_faulted;
#endif
/* When access exceptions happen, we must do this. */
static void clean_and_reenable_l1_caches(void)
static void spitfire_clean_and_reenable_l1_caches(void)
{
unsigned long va;
if (tlb_type == spitfire) {
/* Clean 'em. */
for (va = 0; va < (PAGE_SIZE << 1); va += 32) {
spitfire_put_icache_tag(va, 0x0);
spitfire_put_dcache_tag(va, 0x0);
}
if (tlb_type != spitfire)
BUG();
/* Re-enable in LSU. */
__asm__ __volatile__("flush %%g6\n\t"
"membar #Sync\n\t"
"stxa %0, [%%g0] %1\n\t"
"membar #Sync"
: /* no outputs */
: "r" (LSU_CONTROL_IC | LSU_CONTROL_DC |
LSU_CONTROL_IM | LSU_CONTROL_DM),
"i" (ASI_LSU_CONTROL)
: "memory");
} else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
/* Flush D-cache */
for (va = 0; va < (1 << 16); va += (1 << 5)) {
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync"
: /* no outputs */
: "r" (va), "i" (ASI_DCACHE_TAG));
}
/* Clean 'em. */
for (va = 0; va < (PAGE_SIZE << 1); va += 32) {
spitfire_put_icache_tag(va, 0x0);
spitfire_put_dcache_tag(va, 0x0);
}
/* Re-enable in LSU. */
__asm__ __volatile__("flush %%g6\n\t"
"membar #Sync\n\t"
"stxa %0, [%%g0] %1\n\t"
"membar #Sync"
: /* no outputs */
: "r" (LSU_CONTROL_IC | LSU_CONTROL_DC |
LSU_CONTROL_IM | LSU_CONTROL_DM),
"i" (ASI_LSU_CONTROL)
: "memory");
}
void do_iae(struct pt_regs *regs)
{
siginfo_t info;
clean_and_reenable_l1_caches();
spitfire_clean_and_reenable_l1_caches();
info.si_signo = SIGBUS;
info.si_errno = 0;
......@@ -232,7 +229,7 @@ void do_dae(struct pt_regs *regs)
{
#ifdef CONFIG_PCI
if (pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
clean_and_reenable_l1_caches();
spitfire_clean_and_reenable_l1_caches();
pci_poke_faulted = 1;
......
arch/sparc64/lib/blockops.S
View file @ f9e224eb
......@@ -106,13 +106,8 @@ cheetah_patch_1:
bne,pn %xcc, copy_page_using_blkcommit
nop
rdpr %ver, %g3
sllx %g3, 16, %g3
srlx %g3, 32 + 16, %g3
cmp %g3, 0x14 ! CHEETAH_ID
be,pn %icc, cheetah_copy_user_page
cmp %g3, 0x15 ! CHEETAH_PLUS_ID
bne,pt %icc, spitfire_copy_user_page
BRANCH_IF_ANY_CHEETAH(g3,o2,cheetah_copy_user_page)
ba,pt %xcc, spitfire_copy_user_page
nop
cheetah_copy_user_page:
......
include/asm-sparc64/head.h
View file @ f9e224eb
......@@ -8,7 +8,41 @@
#define PTREGS_OFF (STACK_BIAS + REGWIN_SZ)
#define CHEETAH_ID 0x003e0014
#define CHEETAH_PLUS_ID 0x003e0015
#define __CHEETAH_ID 0x003e0014
#define CHEETAH_MANUF 0x003e
#define CHEETAH_IMPL 0x0014
#define CHEETAH_PLUS_IMPL 0x0015
#define BRANCH_IF_CHEETAH_BASE(tmp1,tmp2,label) \
rdpr %ver, %tmp1; \
sethi %hi(__CHEETAH_ID), %tmp2; \
srlx %tmp1, 32, %tmp1; \
or %tmp2, %lo(__CHEETAH_ID), %tmp2;\
cmp %tmp1, %tmp2; \
be,pn %icc, label; \
nop;
#define BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(tmp1,tmp2,label) \
rdpr %ver, %tmp1; \
srlx %tmp1, (32 + 16), %tmp2; \
cmp %tmp2, CHEETAH_MANUF; \
bne,pt %xcc, 99f; \
sllx %tmp1, 16, %tmp1; \
srlx %tmp1, (32 + 16), %tmp2; \
cmp %tmp2, CHEETAH_PLUS_IMPL; \
bgeu,pt %xcc, label; \
99: nop;
#define BRANCH_IF_ANY_CHEETAH(tmp1,tmp2,label) \
rdpr %ver, %tmp1; \
srlx %tmp1, (32 + 16), %tmp2; \
cmp %tmp2, CHEETAH_MANUF; \
bne,pt %xcc, 99f; \
sllx %tmp1, 16, %tmp1; \
srlx %tmp1, (32 + 16), %tmp2; \
cmp %tmp2, CHEETAH_IMPL; \
bgeu,pt %xcc, label; \
99: nop;
#endif /* !(_SPARC64_HEAD_H) */
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