Commit fad4e18f authored by Vignesh Raghavendra's avatar Vignesh Raghavendra Committed by Nishanth Menon

arm64: dts: ti: k3-am64-main: Add ADC nodes

AM64 SoC has a single ADC IP with 8 channels. Add DT node for the same.

Default usecase is to control ADC from non Linux core on the system on
AM642 GP EVM, therefore mark the node as reserved in k3-am642-evm.dts
file. ADC lines are not pinned out on AM642 SK board, therefore disable
the node in k3-am642-sk.dts file.
Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Reviewed-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210318113443.20036-1-vigneshr@ti.com
parent 04a80a75
......@@ -521,4 +521,21 @@ usb0: usb@f400000{
dr_mode = "otg";
};
};
tscadc0: tscadc@28001000 {
compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
reg = <0x00 0x28001000 0x00 0x1000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 0 0>;
assigned-clocks = <&k3_clks 0 0>;
assigned-clock-parents = <&k3_clks 0 3>;
assigned-clock-rates = <60000000>;
clock-names = "adc_tsc_fck";
adc {
#io-channel-cells = <1>;
compatible = "ti,am654-adc", "ti,am3359-adc";
};
};
};
......@@ -377,3 +377,8 @@ cpsw3g_phy0: ethernet-phy@0 {
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
&tscadc0 {
/* ADC is reserved for R5 usage */
status = "reserved";
};
......@@ -244,3 +244,7 @@ cpsw3g_phy1: ethernet-phy@1 {
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
&tscadc0 {
status = "disabled";
};
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