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Commit fc646236 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Vinod Koul
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phy: qcom-qmp-combo,usb: add support for separate PCS_USB region 

Different QMP USB PHYs might have different offset from PCS to PCS_USB
register space, but the same PCS_USB register layout. Add separate
PCS_USB region space and merge related PCS_USB definitions.
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220705094320.1313312-4-dmitry.baryshkov@linaro.orgSigned-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 2eb2920a
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Inline Side-by-side
Showing with 163 additions and 108 deletions
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
View file @ fc646236
......@@ -155,8 +155,10 @@ static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_START_CTRL] = 0x44,
[QPHY_PCS_STATUS] = 0x14,
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
/* In PCS_USB */
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x008,
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x014,
};
static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
......@@ -451,6 +453,9 @@ static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
};
static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
};
......@@ -520,6 +525,9 @@ static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
};
static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
};
......@@ -634,6 +642,8 @@ struct qmp_phy_cfg {
int rx_tbl_num;
const struct qmp_phy_init_tbl *pcs_tbl;
int pcs_tbl_num;
const struct qmp_phy_init_tbl *pcs_usb_tbl;
int pcs_usb_tbl_num;
/* Init sequence for DP PHY block link rates */
const struct qmp_phy_init_tbl *serdes_tbl_rbr;
......@@ -679,6 +689,10 @@ struct qmp_phy_cfg {
bool has_phy_dp_com_ctrl;
/* true, if PHY has secondary tx/rx lanes to be configured */
bool is_dual_lane_phy;
/* Offset from PCS to PCS_USB region */
unsigned int pcs_usb_offset;
};
struct qmp_phy_combo_cfg {
......@@ -698,6 +712,7 @@ struct qmp_phy_combo_cfg {
* @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
* @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
* @pcs_misc: iomapped memory space for lane's pcs_misc
* @pcs_usb: iomapped memory space for lane's pcs_usb
* @pipe_clk: pipe clock
* @index: lane index
* @qmp: QMP phy to which this lane belongs
......@@ -717,6 +732,7 @@ struct qmp_phy {
void __iomem *tx2;
void __iomem *rx2;
void __iomem *pcs_misc;
void __iomem *pcs_usb;
struct clk *pipe_clk;
unsigned int index;
struct qcom_qmp *qmp;
......@@ -905,6 +921,8 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
.rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
.pcs_tbl = sm8150_usb3_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
.pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl,
.pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl),
.clk_list = qmp_v4_phy_clk_l,
.num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
......@@ -912,6 +930,7 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.regs = qmp_v4_usb3phy_regs_layout,
.pcs_usb_offset = 0x300,
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
......@@ -978,6 +997,8 @@ static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
.rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
.pcs_tbl = sm8250_usb3_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
.pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl,
.pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl),
.clk_list = qmp_v4_sm8250_usbphy_clk_l,
.num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
......@@ -985,6 +1006,7 @@ static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.regs = qmp_v4_usb3phy_regs_layout,
.pcs_usb_offset = 0x300,
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
......@@ -1869,7 +1891,7 @@ static int qcom_qmp_phy_combo_set_mode(struct phy *phy,
static void qcom_qmp_phy_combo_enable_autonomous_mode(struct qmp_phy *qphy)
{
const struct qmp_phy_cfg *cfg = qphy->cfg;
void __iomem *pcs = qphy->pcs;
void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs;
void __iomem *pcs_misc = qphy->pcs_misc;
u32 intr_mask;
......@@ -1880,15 +1902,15 @@ static void qcom_qmp_phy_combo_enable_autonomous_mode(struct qmp_phy *qphy)
intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
/* Clear any pending interrupts status */
qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
/* Writing 1 followed by 0 clears the interrupt */
qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
/* Enable required PHY autonomous mode interrupts */
qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
/* Enable i/o clamp_n for autonomous mode */
if (pcs_misc)
......@@ -1898,19 +1920,19 @@ static void qcom_qmp_phy_combo_enable_autonomous_mode(struct qmp_phy *qphy)
static void qcom_qmp_phy_combo_disable_autonomous_mode(struct qmp_phy *qphy)
{
const struct qmp_phy_cfg *cfg = qphy->cfg;
void __iomem *pcs = qphy->pcs;
void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs_usb;
void __iomem *pcs_misc = qphy->pcs_misc;
/* Disable i/o clamp_n on resume for normal mode */
if (pcs_misc)
qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
/* Writing 1 followed by 0 clears the interrupt */
qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
}
static int __maybe_unused qcom_qmp_phy_combo_runtime_suspend(struct device *dev)
......@@ -2346,6 +2368,9 @@ int qcom_qmp_phy_combo_create(struct device *dev, struct device_node *np, int id
if (!qphy->pcs)
return -ENOMEM;
if (cfg->pcs_usb_offset)
qphy->pcs_usb = qphy->pcs + cfg->pcs_usb_offset;
/*
* If this is a dual-lane PHY, then there should be registers for the
* second lane. Some old device trees did not specify this, so fall
......
drivers/phy/qualcomm/phy-qcom-qmp-usb.c
View file @ fc646236
This diff is collapsed.
drivers/phy/qualcomm/phy-qcom-qmp.h
View file @ fc646236
......@@ -1006,29 +1006,31 @@
#define QPHY_V4_PCS_EQ_CONFIG3 0x1e4
#define QPHY_V4_PCS_EQ_CONFIG4 0x1e8
#define QPHY_V4_PCS_EQ_CONFIG5 0x1ec
#define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x300
#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304
#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308
#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c
#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310
#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314
#define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318
#define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x31c
#define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x320
#define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324
#define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x328
#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x32c
#define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x330
#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x334
#define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x338
#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x33c
#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x340
#define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x344
#define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x348
#define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x34c
#define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x350
#define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x354
#define QPHY_V4_PCS_USB3_TEST_CONTROL 0x358
/* Only for QMP V4 PHY - USB3 PCS registers */
#define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x000
#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
#define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
#define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x01c
#define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
#define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
#define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x028
#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x02c
#define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x030
#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x034
#define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x038
#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x03c
#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x040
#define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x044
#define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x048
#define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x04c
#define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x050
#define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x054
#define QPHY_V4_PCS_USB3_TEST_CONTROL 0x058
/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */
#define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188
......@@ -1036,10 +1038,6 @@
#define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0
#define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4
/* Only for QMP V4 PHY - UNI has 0x300 offset for PCS_USB3 regs */
#define QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x618
#define QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x638
/* Only for QMP V4 PHY - PCS_MISC registers */
#define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00
#define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04
......@@ -1290,34 +1288,30 @@
#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
/* Only for QMP V5 PHY - USB3 have different offsets than V4 */
#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x300
#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304
#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308
#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c
#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310
#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314
#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318
#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x31c
#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x320
#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324
#define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x328
#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x32c
#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x330
#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x334
#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x338
#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x33c
#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x340
#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x344
#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x348
#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x34c
#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x350
#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x354
#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x358
#define QPHY_V5_PCS_USB3_TEST_CONTROL 0x35c
#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x360
/* Only for QMP V5 PHY - UNI has 0x1000 offset for PCS_USB3 regs */
#define QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x1018
#define QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x103c
#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000
#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c
#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
#define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x028
#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x02c
#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x030
#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x034
#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x038
#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x03c
#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x040
#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x044
#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x048
#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x04c
#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x050
#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x054
#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x058
#define QPHY_V5_PCS_USB3_TEST_CONTROL 0x05c
#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x060
#endif
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