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Commit ff4d0241 authored by Vinod Koul's avatar Vinod Koul
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Merge commit 'renesas-shdma-for-v3.17' into for-linus

parents dd8ecfca 0cdbee33
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arch/sh/drivers/dma/dma-sh.c
View file @ ff4d0241
...@@ -25,7 +25,7 @@ ...@@ -25,7 +25,7 @@
* Define the default configuration for dual address memory-memory transfer. * Define the default configuration for dual address memory-memory transfer.
* The 0x400 value represents auto-request, external->external. * The 0x400 value represents auto-request, external->external.
*/ */
#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_INDEX2VAL(XMIT_SZ_32BIT)) #define RS_DUAL (DM_INC | SM_INC | RS_AUTO | TS_INDEX2VAL(XMIT_SZ_32BIT))
static unsigned long dma_find_base(unsigned int chan) static unsigned long dma_find_base(unsigned int chan)
{ {
......
arch/sh/include/asm/dma-register.h
View file @ ff4d0241
...@@ -13,17 +13,17 @@ ...@@ -13,17 +13,17 @@
#ifndef DMA_REGISTER_H #ifndef DMA_REGISTER_H
#define DMA_REGISTER_H #define DMA_REGISTER_H
/* DMA register */ /* DMA registers */
#define SAR 0x00 #define SAR 0x00 /* Source Address Register */
#define DAR 0x04 #define DAR 0x04 /* Destination Address Register */
#define TCR 0x08 #define TCR 0x08 /* Transfer Count Register */
#define CHCR 0x0C #define CHCR 0x0C /* Channel Control Register */
#define DMAOR 0x40 #define DMAOR 0x40 /* DMA Operation Register */
/* DMAOR definitions */ /* DMAOR definitions */
#define DMAOR_AE 0x00000004 #define DMAOR_AE 0x00000004 /* Address Error Flag */
#define DMAOR_NMIF 0x00000002 #define DMAOR_NMIF 0x00000002
#define DMAOR_DME 0x00000001 #define DMAOR_DME 0x00000001 /* DMA Master Enable */
/* Definitions for the SuperH DMAC */ /* Definitions for the SuperH DMAC */
#define REQ_L 0x00000000 #define REQ_L 0x00000000
...@@ -34,18 +34,20 @@ ...@@ -34,18 +34,20 @@
#define ACK_W 0x00020000 #define ACK_W 0x00020000
#define ACK_H 0x00000000 #define ACK_H 0x00000000
#define ACK_L 0x00010000 #define ACK_L 0x00010000
#define DM_INC 0x00004000 #define DM_INC 0x00004000 /* Destination addresses are incremented */
#define DM_DEC 0x00008000 #define DM_DEC 0x00008000 /* Destination addresses are decremented */
#define DM_FIX 0x0000c000 #define DM_FIX 0x0000c000 /* Destination address is fixed */
#define SM_INC 0x00001000 #define SM_INC 0x00001000 /* Source addresses are incremented */
#define SM_DEC 0x00002000 #define SM_DEC 0x00002000 /* Source addresses are decremented */
#define SM_FIX 0x00003000 #define SM_FIX 0x00003000 /* Source address is fixed */
#define RS_IN 0x00000200 #define RS_IN 0x00000200
#define RS_OUT 0x00000300 #define RS_OUT 0x00000300
#define RS_AUTO 0x00000400 /* Auto Request */
#define RS_ERS 0x00000800 /* DMA extended resource selector */
#define TS_BLK 0x00000040 #define TS_BLK 0x00000040
#define TM_BUR 0x00000020 #define TM_BUR 0x00000020
#define CHCR_DE 0x00000001 #define CHCR_DE 0x00000001 /* DMA Enable */
#define CHCR_TE 0x00000002 #define CHCR_TE 0x00000002 /* Transfer End Flag */
#define CHCR_IE 0x00000004 #define CHCR_IE 0x00000004 /* Interrupt Enable */
#endif #endif
arch/sh/kernel/cpu/sh4a/setup-sh7722.c
View file @ ff4d0241
...@@ -30,62 +30,62 @@ static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = { ...@@ -30,62 +30,62 @@ static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
{ {
.slave_id = SHDMA_SLAVE_SCIF0_TX, .slave_id = SHDMA_SLAVE_SCIF0_TX,
.addr = 0xffe0000c, .addr = 0xffe0000c,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x21, .mid_rid = 0x21,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF0_RX, .slave_id = SHDMA_SLAVE_SCIF0_RX,
.addr = 0xffe00014, .addr = 0xffe00014,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x22, .mid_rid = 0x22,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF1_TX, .slave_id = SHDMA_SLAVE_SCIF1_TX,
.addr = 0xffe1000c, .addr = 0xffe1000c,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x25, .mid_rid = 0x25,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF1_RX, .slave_id = SHDMA_SLAVE_SCIF1_RX,
.addr = 0xffe10014, .addr = 0xffe10014,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x26, .mid_rid = 0x26,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF2_TX, .slave_id = SHDMA_SLAVE_SCIF2_TX,
.addr = 0xffe2000c, .addr = 0xffe2000c,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x29, .mid_rid = 0x29,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF2_RX, .slave_id = SHDMA_SLAVE_SCIF2_RX,
.addr = 0xffe20014, .addr = 0xffe20014,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x2a, .mid_rid = 0x2a,
}, { }, {
.slave_id = SHDMA_SLAVE_SIUA_TX, .slave_id = SHDMA_SLAVE_SIUA_TX,
.addr = 0xa454c098, .addr = 0xa454c098,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
.mid_rid = 0xb1, .mid_rid = 0xb1,
}, { }, {
.slave_id = SHDMA_SLAVE_SIUA_RX, .slave_id = SHDMA_SLAVE_SIUA_RX,
.addr = 0xa454c090, .addr = 0xa454c090,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
.mid_rid = 0xb2, .mid_rid = 0xb2,
}, { }, {
.slave_id = SHDMA_SLAVE_SIUB_TX, .slave_id = SHDMA_SLAVE_SIUB_TX,
.addr = 0xa454c09c, .addr = 0xa454c09c,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
.mid_rid = 0xb5, .mid_rid = 0xb5,
}, { }, {
.slave_id = SHDMA_SLAVE_SIUB_RX, .slave_id = SHDMA_SLAVE_SIUB_RX,
.addr = 0xa454c094, .addr = 0xa454c094,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
.mid_rid = 0xb6, .mid_rid = 0xb6,
}, { }, {
.slave_id = SHDMA_SLAVE_SDHI0_TX, .slave_id = SHDMA_SLAVE_SDHI0_TX,
.addr = 0x04ce0030, .addr = 0x04ce0030,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
.mid_rid = 0xc1, .mid_rid = 0xc1,
}, { }, {
.slave_id = SHDMA_SLAVE_SDHI0_RX, .slave_id = SHDMA_SLAVE_SDHI0_RX,
.addr = 0x04ce0030, .addr = 0x04ce0030,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
.mid_rid = 0xc2, .mid_rid = 0xc2,
}, },
}; };
......
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
View file @ ff4d0241
...@@ -36,122 +36,122 @@ static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = { ...@@ -36,122 +36,122 @@ static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = {
{ {
.slave_id = SHDMA_SLAVE_SCIF0_TX, .slave_id = SHDMA_SLAVE_SCIF0_TX,
.addr = 0xffe0000c, .addr = 0xffe0000c,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x21, .mid_rid = 0x21,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF0_RX, .slave_id = SHDMA_SLAVE_SCIF0_RX,
.addr = 0xffe00014, .addr = 0xffe00014,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x22, .mid_rid = 0x22,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF1_TX, .slave_id = SHDMA_SLAVE_SCIF1_TX,
.addr = 0xffe1000c, .addr = 0xffe1000c,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x25, .mid_rid = 0x25,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF1_RX, .slave_id = SHDMA_SLAVE_SCIF1_RX,
.addr = 0xffe10014, .addr = 0xffe10014,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x26, .mid_rid = 0x26,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF2_TX, .slave_id = SHDMA_SLAVE_SCIF2_TX,
.addr = 0xffe2000c, .addr = 0xffe2000c,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x29, .mid_rid = 0x29,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF2_RX, .slave_id = SHDMA_SLAVE_SCIF2_RX,
.addr = 0xffe20014, .addr = 0xffe20014,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x2a, .mid_rid = 0x2a,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF3_TX, .slave_id = SHDMA_SLAVE_SCIF3_TX,
.addr = 0xa4e30020, .addr = 0xa4e30020,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x2d, .mid_rid = 0x2d,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF3_RX, .slave_id = SHDMA_SLAVE_SCIF3_RX,
.addr = 0xa4e30024, .addr = 0xa4e30024,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x2e, .mid_rid = 0x2e,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF4_TX, .slave_id = SHDMA_SLAVE_SCIF4_TX,
.addr = 0xa4e40020, .addr = 0xa4e40020,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x31, .mid_rid = 0x31,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF4_RX, .slave_id = SHDMA_SLAVE_SCIF4_RX,
.addr = 0xa4e40024, .addr = 0xa4e40024,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x32, .mid_rid = 0x32,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF5_TX, .slave_id = SHDMA_SLAVE_SCIF5_TX,
.addr = 0xa4e50020, .addr = 0xa4e50020,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x35, .mid_rid = 0x35,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF5_RX, .slave_id = SHDMA_SLAVE_SCIF5_RX,
.addr = 0xa4e50024, .addr = 0xa4e50024,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x36, .mid_rid = 0x36,
}, { }, {
.slave_id = SHDMA_SLAVE_USB0D0_TX, .slave_id = SHDMA_SLAVE_USB0D0_TX,
.addr = 0xA4D80100, .addr = 0xA4D80100,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
.mid_rid = 0x73, .mid_rid = 0x73,
}, { }, {
.slave_id = SHDMA_SLAVE_USB0D0_RX, .slave_id = SHDMA_SLAVE_USB0D0_RX,
.addr = 0xA4D80100, .addr = 0xA4D80100,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
.mid_rid = 0x73, .mid_rid = 0x73,
}, { }, {
.slave_id = SHDMA_SLAVE_USB0D1_TX, .slave_id = SHDMA_SLAVE_USB0D1_TX,
.addr = 0xA4D80120, .addr = 0xA4D80120,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
.mid_rid = 0x77, .mid_rid = 0x77,
}, { }, {
.slave_id = SHDMA_SLAVE_USB0D1_RX, .slave_id = SHDMA_SLAVE_USB0D1_RX,
.addr = 0xA4D80120, .addr = 0xA4D80120,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
.mid_rid = 0x77, .mid_rid = 0x77,
}, { }, {
.slave_id = SHDMA_SLAVE_USB1D0_TX, .slave_id = SHDMA_SLAVE_USB1D0_TX,
.addr = 0xA4D90100, .addr = 0xA4D90100,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
.mid_rid = 0xab, .mid_rid = 0xab,
}, { }, {
.slave_id = SHDMA_SLAVE_USB1D0_RX, .slave_id = SHDMA_SLAVE_USB1D0_RX,
.addr = 0xA4D90100, .addr = 0xA4D90100,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
.mid_rid = 0xab, .mid_rid = 0xab,
}, { }, {
.slave_id = SHDMA_SLAVE_USB1D1_TX, .slave_id = SHDMA_SLAVE_USB1D1_TX,
.addr = 0xA4D90120, .addr = 0xA4D90120,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
.mid_rid = 0xaf, .mid_rid = 0xaf,
}, { }, {
.slave_id = SHDMA_SLAVE_USB1D1_RX, .slave_id = SHDMA_SLAVE_USB1D1_RX,
.addr = 0xA4D90120, .addr = 0xA4D90120,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
.mid_rid = 0xaf, .mid_rid = 0xaf,
}, { }, {
.slave_id = SHDMA_SLAVE_SDHI0_TX, .slave_id = SHDMA_SLAVE_SDHI0_TX,
.addr = 0x04ce0030, .addr = 0x04ce0030,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
.mid_rid = 0xc1, .mid_rid = 0xc1,
}, { }, {
.slave_id = SHDMA_SLAVE_SDHI0_RX, .slave_id = SHDMA_SLAVE_SDHI0_RX,
.addr = 0x04ce0030, .addr = 0x04ce0030,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
.mid_rid = 0xc2, .mid_rid = 0xc2,
}, { }, {
.slave_id = SHDMA_SLAVE_SDHI1_TX, .slave_id = SHDMA_SLAVE_SDHI1_TX,
.addr = 0x04cf0030, .addr = 0x04cf0030,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
.mid_rid = 0xc9, .mid_rid = 0xc9,
}, { }, {
.slave_id = SHDMA_SLAVE_SDHI1_RX, .slave_id = SHDMA_SLAVE_SDHI1_RX,
.addr = 0x04cf0030, .addr = 0x04cf0030,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
.mid_rid = 0xca, .mid_rid = 0xca,
}, },
}; };
......
arch/sh/kernel/cpu/sh4a/setup-sh7757.c
View file @ ff4d0241
...@@ -123,28 +123,28 @@ static const struct sh_dmae_slave_config sh7757_dmae0_slaves[] = { ...@@ -123,28 +123,28 @@ static const struct sh_dmae_slave_config sh7757_dmae0_slaves[] = {
{ {
.slave_id = SHDMA_SLAVE_SDHI_TX, .slave_id = SHDMA_SLAVE_SDHI_TX,
.addr = 0x1fe50030, .addr = 0x1fe50030,
.chcr = SM_INC | 0x800 | 0x40000000 | .chcr = SM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_16BIT), TS_INDEX2VAL(XMIT_SZ_16BIT),
.mid_rid = 0xc5, .mid_rid = 0xc5,
}, },
{ {
.slave_id = SHDMA_SLAVE_SDHI_RX, .slave_id = SHDMA_SLAVE_SDHI_RX,
.addr = 0x1fe50030, .addr = 0x1fe50030,
.chcr = DM_INC | 0x800 | 0x40000000 | .chcr = DM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_16BIT), TS_INDEX2VAL(XMIT_SZ_16BIT),
.mid_rid = 0xc6, .mid_rid = 0xc6,
}, },
{ {
.slave_id = SHDMA_SLAVE_MMCIF_TX, .slave_id = SHDMA_SLAVE_MMCIF_TX,
.addr = 0x1fcb0034, .addr = 0x1fcb0034,
.chcr = SM_INC | 0x800 | 0x40000000 | .chcr = SM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_32BIT), TS_INDEX2VAL(XMIT_SZ_32BIT),
.mid_rid = 0xd3, .mid_rid = 0xd3,
}, },
{ {
.slave_id = SHDMA_SLAVE_MMCIF_RX, .slave_id = SHDMA_SLAVE_MMCIF_RX,
.addr = 0x1fcb0034, .addr = 0x1fcb0034,
.chcr = DM_INC | 0x800 | 0x40000000 | .chcr = DM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_32BIT), TS_INDEX2VAL(XMIT_SZ_32BIT),
.mid_rid = 0xd7, .mid_rid = 0xd7,
}, },
...@@ -154,56 +154,56 @@ static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = { ...@@ -154,56 +154,56 @@ static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = {
{ {
.slave_id = SHDMA_SLAVE_SCIF2_TX, .slave_id = SHDMA_SLAVE_SCIF2_TX,
.addr = 0x1f4b000c, .addr = 0x1f4b000c,
.chcr = SM_INC | 0x800 | 0x40000000 | .chcr = SM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x21, .mid_rid = 0x21,
}, },
{ {
.slave_id = SHDMA_SLAVE_SCIF2_RX, .slave_id = SHDMA_SLAVE_SCIF2_RX,
.addr = 0x1f4b0014, .addr = 0x1f4b0014,
.chcr = DM_INC | 0x800 | 0x40000000 | .chcr = DM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x22, .mid_rid = 0x22,
}, },
{ {
.slave_id = SHDMA_SLAVE_SCIF3_TX, .slave_id = SHDMA_SLAVE_SCIF3_TX,
.addr = 0x1f4c000c, .addr = 0x1f4c000c,
.chcr = SM_INC | 0x800 | 0x40000000 | .chcr = SM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x29, .mid_rid = 0x29,
}, },
{ {
.slave_id = SHDMA_SLAVE_SCIF3_RX, .slave_id = SHDMA_SLAVE_SCIF3_RX,
.addr = 0x1f4c0014, .addr = 0x1f4c0014,
.chcr = DM_INC | 0x800 | 0x40000000 | .chcr = DM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x2a, .mid_rid = 0x2a,
}, },
{ {
.slave_id = SHDMA_SLAVE_SCIF4_TX, .slave_id = SHDMA_SLAVE_SCIF4_TX,
.addr = 0x1f4d000c, .addr = 0x1f4d000c,
.chcr = SM_INC | 0x800 | 0x40000000 | .chcr = SM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x41, .mid_rid = 0x41,
}, },
{ {
.slave_id = SHDMA_SLAVE_SCIF4_RX, .slave_id = SHDMA_SLAVE_SCIF4_RX,
.addr = 0x1f4d0014, .addr = 0x1f4d0014,
.chcr = DM_INC | 0x800 | 0x40000000 | .chcr = DM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x42, .mid_rid = 0x42,
}, },
{ {
.slave_id = SHDMA_SLAVE_RSPI_TX, .slave_id = SHDMA_SLAVE_RSPI_TX,
.addr = 0xfe480004, .addr = 0xfe480004,
.chcr = SM_INC | 0x800 | 0x40000000 | .chcr = SM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_16BIT), TS_INDEX2VAL(XMIT_SZ_16BIT),
.mid_rid = 0xc1, .mid_rid = 0xc1,
}, },
{ {
.slave_id = SHDMA_SLAVE_RSPI_RX, .slave_id = SHDMA_SLAVE_RSPI_RX,
.addr = 0xfe480004, .addr = 0xfe480004,
.chcr = DM_INC | 0x800 | 0x40000000 | .chcr = DM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_16BIT), TS_INDEX2VAL(XMIT_SZ_16BIT),
.mid_rid = 0xc2, .mid_rid = 0xc2,
}, },
...@@ -213,70 +213,70 @@ static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = { ...@@ -213,70 +213,70 @@ static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = {
{ {
.slave_id = SHDMA_SLAVE_RIIC0_TX, .slave_id = SHDMA_SLAVE_RIIC0_TX,
.addr = 0x1e500012, .addr = 0x1e500012,
.chcr = SM_INC | 0x800 | 0x40000000 | .chcr = SM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x21, .mid_rid = 0x21,
}, },
{ {
.slave_id = SHDMA_SLAVE_RIIC0_RX, .slave_id = SHDMA_SLAVE_RIIC0_RX,
.addr = 0x1e500013, .addr = 0x1e500013,
.chcr = DM_INC | 0x800 | 0x40000000 | .chcr = DM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x22, .mid_rid = 0x22,
}, },
{ {
.slave_id = SHDMA_SLAVE_RIIC1_TX, .slave_id = SHDMA_SLAVE_RIIC1_TX,
.addr = 0x1e510012, .addr = 0x1e510012,
.chcr = SM_INC | 0x800 | 0x40000000 | .chcr = SM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x29, .mid_rid = 0x29,
}, },
{ {
.slave_id = SHDMA_SLAVE_RIIC1_RX, .slave_id = SHDMA_SLAVE_RIIC1_RX,
.addr = 0x1e510013, .addr = 0x1e510013,
.chcr = DM_INC | 0x800 | 0x40000000 | .chcr = DM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x2a, .mid_rid = 0x2a,
}, },
{ {
.slave_id = SHDMA_SLAVE_RIIC2_TX, .slave_id = SHDMA_SLAVE_RIIC2_TX,
.addr = 0x1e520012, .addr = 0x1e520012,
.chcr = SM_INC | 0x800 | 0x40000000 | .chcr = SM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0xa1, .mid_rid = 0xa1,
}, },
{ {
.slave_id = SHDMA_SLAVE_RIIC2_RX, .slave_id = SHDMA_SLAVE_RIIC2_RX,
.addr = 0x1e520013, .addr = 0x1e520013,
.chcr = DM_INC | 0x800 | 0x40000000 | .chcr = DM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0xa2, .mid_rid = 0xa2,
}, },
{ {
.slave_id = SHDMA_SLAVE_RIIC3_TX, .slave_id = SHDMA_SLAVE_RIIC3_TX,
.addr = 0x1e530012, .addr = 0x1e530012,
.chcr = SM_INC | 0x800 | 0x40000000 | .chcr = SM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0xa9, .mid_rid = 0xa9,
}, },
{ {
.slave_id = SHDMA_SLAVE_RIIC3_RX, .slave_id = SHDMA_SLAVE_RIIC3_RX,
.addr = 0x1e530013, .addr = 0x1e530013,
.chcr = DM_INC | 0x800 | 0x40000000 | .chcr = DM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0xaf, .mid_rid = 0xaf,
}, },
{ {
.slave_id = SHDMA_SLAVE_RIIC4_TX, .slave_id = SHDMA_SLAVE_RIIC4_TX,
.addr = 0x1e540012, .addr = 0x1e540012,
.chcr = SM_INC | 0x800 | 0x40000000 | .chcr = SM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0xc5, .mid_rid = 0xc5,
}, },
{ {
.slave_id = SHDMA_SLAVE_RIIC4_RX, .slave_id = SHDMA_SLAVE_RIIC4_RX,
.addr = 0x1e540013, .addr = 0x1e540013,
.chcr = DM_INC | 0x800 | 0x40000000 | .chcr = DM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0xc6, .mid_rid = 0xc6,
}, },
...@@ -286,70 +286,70 @@ static const struct sh_dmae_slave_config sh7757_dmae3_slaves[] = { ...@@ -286,70 +286,70 @@ static const struct sh_dmae_slave_config sh7757_dmae3_slaves[] = {
{ {
.slave_id = SHDMA_SLAVE_RIIC5_TX, .slave_id = SHDMA_SLAVE_RIIC5_TX,
.addr = 0x1e550012, .addr = 0x1e550012,
.chcr = SM_INC | 0x800 | 0x40000000 | .chcr = SM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x21, .mid_rid = 0x21,
}, },
{ {
.slave_id = SHDMA_SLAVE_RIIC5_RX, .slave_id = SHDMA_SLAVE_RIIC5_RX,
.addr = 0x1e550013, .addr = 0x1e550013,
.chcr = DM_INC | 0x800 | 0x40000000 | .chcr = DM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x22, .mid_rid = 0x22,
}, },
{ {
.slave_id = SHDMA_SLAVE_RIIC6_TX, .slave_id = SHDMA_SLAVE_RIIC6_TX,
.addr = 0x1e560012, .addr = 0x1e560012,
.chcr = SM_INC | 0x800 | 0x40000000 | .chcr = SM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x29, .mid_rid = 0x29,
}, },
{ {
.slave_id = SHDMA_SLAVE_RIIC6_RX, .slave_id = SHDMA_SLAVE_RIIC6_RX,
.addr = 0x1e560013, .addr = 0x1e560013,
.chcr = DM_INC | 0x800 | 0x40000000 | .chcr = DM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x2a, .mid_rid = 0x2a,
}, },
{ {
.slave_id = SHDMA_SLAVE_RIIC7_TX, .slave_id = SHDMA_SLAVE_RIIC7_TX,
.addr = 0x1e570012, .addr = 0x1e570012,
.chcr = SM_INC | 0x800 | 0x40000000 | .chcr = SM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x41, .mid_rid = 0x41,
}, },
{ {
.slave_id = SHDMA_SLAVE_RIIC7_RX, .slave_id = SHDMA_SLAVE_RIIC7_RX,
.addr = 0x1e570013, .addr = 0x1e570013,
.chcr = DM_INC | 0x800 | 0x40000000 | .chcr = DM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x42, .mid_rid = 0x42,
}, },
{ {
.slave_id = SHDMA_SLAVE_RIIC8_TX, .slave_id = SHDMA_SLAVE_RIIC8_TX,
.addr = 0x1e580012, .addr = 0x1e580012,
.chcr = SM_INC | 0x800 | 0x40000000 | .chcr = SM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x45, .mid_rid = 0x45,
}, },
{ {
.slave_id = SHDMA_SLAVE_RIIC8_RX, .slave_id = SHDMA_SLAVE_RIIC8_RX,
.addr = 0x1e580013, .addr = 0x1e580013,
.chcr = DM_INC | 0x800 | 0x40000000 | .chcr = DM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x46, .mid_rid = 0x46,
}, },
{ {
.slave_id = SHDMA_SLAVE_RIIC9_TX, .slave_id = SHDMA_SLAVE_RIIC9_TX,
.addr = 0x1e590012, .addr = 0x1e590012,
.chcr = SM_INC | 0x800 | 0x40000000 | .chcr = SM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x51, .mid_rid = 0x51,
}, },
{ {
.slave_id = SHDMA_SLAVE_RIIC9_RX, .slave_id = SHDMA_SLAVE_RIIC9_RX,
.addr = 0x1e590013, .addr = 0x1e590013,
.chcr = DM_INC | 0x800 | 0x40000000 | .chcr = DM_INC | RS_ERS | 0x40000000 |
TS_INDEX2VAL(XMIT_SZ_8BIT), TS_INDEX2VAL(XMIT_SZ_8BIT),
.mid_rid = 0x52, .mid_rid = 0x52,
}, },
......
drivers/dma/sh/shdma-arm.h
View file @ ff4d0241
...@@ -45,7 +45,7 @@ enum { ...@@ -45,7 +45,7 @@ enum {
((((i) & TS_LOW_BIT) << TS_LOW_SHIFT) |\ ((((i) & TS_LOW_BIT) << TS_LOW_SHIFT) |\
(((i) & TS_HI_BIT) << TS_HI_SHIFT)) (((i) & TS_HI_BIT) << TS_HI_SHIFT))
#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz))) #define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL((xmit_sz)))
#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz))) #define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL((xmit_sz)))
#endif #endif
drivers/dma/sh/shdmac.c
View file @ ff4d0241
...@@ -38,12 +38,12 @@ ...@@ -38,12 +38,12 @@
#include "../dmaengine.h" #include "../dmaengine.h"
#include "shdma.h" #include "shdma.h"
/* DMA register */ /* DMA registers */
#define SAR 0x00 #define SAR 0x00 /* Source Address Register */
#define DAR 0x04 #define DAR 0x04 /* Destination Address Register */
#define TCR 0x08 #define TCR 0x08 /* Transfer Count Register */
#define CHCR 0x0C #define CHCR 0x0C /* Channel Control Register */
#define DMAOR 0x40 #define DMAOR 0x40 /* DMA Operation Register */
#define TEND 0x18 /* USB-DMAC */ #define TEND 0x18 /* USB-DMAC */
...@@ -239,9 +239,8 @@ static void dmae_init(struct sh_dmae_chan *sh_chan) ...@@ -239,9 +239,8 @@ static void dmae_init(struct sh_dmae_chan *sh_chan)
{ {
/* /*
* Default configuration for dual address memory-memory transfer. * Default configuration for dual address memory-memory transfer.
* 0x400 represents auto-request.
*/ */
u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan, u32 chcr = DM_INC | SM_INC | RS_AUTO | log2size_to_chcr(sh_chan,
LOG2_DEFAULT_XFER_SIZE); LOG2_DEFAULT_XFER_SIZE);
sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr); sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
chcr_write(sh_chan, chcr); chcr_write(sh_chan, chcr);
......
include/linux/sh_dma.h
View file @ ff4d0241
...@@ -95,19 +95,21 @@ struct sh_dmae_pdata { ...@@ -95,19 +95,21 @@ struct sh_dmae_pdata {
}; };
/* DMAOR definitions */ /* DMAOR definitions */
#define DMAOR_AE 0x00000004 #define DMAOR_AE 0x00000004 /* Address Error Flag */
#define DMAOR_NMIF 0x00000002 #define DMAOR_NMIF 0x00000002
#define DMAOR_DME 0x00000001 #define DMAOR_DME 0x00000001 /* DMA Master Enable */
/* Definitions for the SuperH DMAC */ /* Definitions for the SuperH DMAC */
#define DM_INC 0x00004000 #define DM_INC 0x00004000 /* Destination addresses are incremented */
#define DM_DEC 0x00008000 #define DM_DEC 0x00008000 /* Destination addresses are decremented */
#define DM_FIX 0x0000c000 #define DM_FIX 0x0000c000 /* Destination address is fixed */
#define SM_INC 0x00001000 #define SM_INC 0x00001000 /* Source addresses are incremented */
#define SM_DEC 0x00002000 #define SM_DEC 0x00002000 /* Source addresses are decremented */
#define SM_FIX 0x00003000 #define SM_FIX 0x00003000 /* Source address is fixed */
#define CHCR_DE 0x00000001 #define RS_AUTO 0x00000400 /* Auto Request */
#define CHCR_TE 0x00000002 #define RS_ERS 0x00000800 /* DMA extended resource selector */
#define CHCR_IE 0x00000004 #define CHCR_DE 0x00000001 /* DMA Enable */
#define CHCR_TE 0x00000002 /* Transfer End Flag */
#define CHCR_IE 0x00000004 /* Interrupt Enable */
#endif #endif
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