- 29 Sep, 2021 11 commits
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Arnd Bergmann authored
The two AMD drivers have their own custom offsetof() implementation that now triggers a warning with recent versions of clang: drivers/gpu/drm/radeon/radeon_atombios.c:133:14: error: performing pointer subtraction with a null pointer has undefined behavior [-Werror,-Wnull-pointer-subtraction] Change all the instances to use the normal offsetof() provided by the kernel that does not have this problem. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Yang Li authored
Use resource_size function on resource object instead of explicit computation. Clean up coccicheck warning: ./drivers/gpu/drm/amd/amdkfd/kfd_migrate.c:905:10-13: ERROR: Missing resource_size with res Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Reviewed-by:
Amos Kong <kongjianjun@gmail.com> Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Arnd Bergmann authored
The overflow check in amdgpu_bo_list_create() causes a warning with clang-14 on 64-bit architectures, since the limit can never be exceeded. drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:74:18: error: result of comparison of constant 256204778801521549 with expression of type 'unsigned int' is always false [-Werror,-Wtautological-constant-out-of-range-compare] if (num_entries > (SIZE_MAX - sizeof(struct amdgpu_bo_list)) ~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The check remains useful for 32-bit architectures, so just avoid the warning by using size_t as the type for the count. Fixes: 920990cb ("drm/amdgpu: allocate the bo_list array after the list") Reviewed-by:Christian König <christian.koenig@amd.com> Signed-off-by:
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Simon Ser authored
On GFX9+, format modifiers are always enabled and ensure the frame-buffers can be scanned out at ADDFB2 time. On GFX8-, format modifiers are not supported and no other check is performed. This means ADDFB2 IOCTLs will succeed even if the tiling isn't supported for scan-out, and will result in garbage displayed on screen [1]. Fix this by adding a check for tiling flags for GFX8 and older. The check is taken from radeonsi in Mesa (see how is_displayable is populated in gfx6_compute_surface). Changes in v2: use drm_WARN_ONCE instead of drm_WARN (Michel) [1]: https://github.com/swaywm/wlroots/issues/3185Signed-off-by:
Simon Ser <contact@emersion.fr> Acked-by:
Michel Dänzer <mdaenzer@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <hwentlan@amd.com> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Cc: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
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Tom St Denis authored
The commit 2766534b added the offset header but didn't add the masks. This adds the masks based on what was selected for the offsets. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Acked-by:
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Charlene Liu authored
[why] pci deviceid not passed to dal dc, without proper break, dcn2.x falls into dcn3.x code path [how] pass in pci deviceid, and break once dal_version initialized. Reviewed-by:
Zhan Liu <Zhan.Liu@amd.com> Acked-by:
Anson Jacob <Anson.Jacob@amd.com> Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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George Shen authored
[Why] Recently debugging efforts have involved setting/checking the X.Y value used during payload allocation. Current output for Y was calculated with incorrect bitshift. Y value is also not human readable. [How] Refactor logging into separate function. Fix Y calculation error and format output to be human readable. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
George Shen <george.shen@amd.com> Tested-by:
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George Shen authored
[Why/How] Theoretically rare corner case where ceil(Y) results in rounding up to an integer. If this happens, the 1 should be carried over to the X value. Reviewed-by:
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Wenjing Liu authored
[why] There is a chance verified link cap can be greater than max link cap. This causes software hang because we cannot power up PHY with link rate that cannot handle. The change is to guard verfieid link cap from becoming larger than max link cap our PHy can support. Reviewed-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Acked-by:
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Josip Pavic authored
[Why] Stack variable params.backlight_ramping_override is uninitialized, so it contains junk data [How] Initialize the variable to false Reviewed-by:
Roman Li <Roman.Li@amd.com> Acked-by:
Josip Pavic <Josip.Pavic@amd.com> Tested-by:
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Michael Strauss authored
[WHY] Blnd, 3dlut, and shaper LUT select registers are double buffered, however their accompanying LUT memory shutdown registers are not. As a result, shutting down LUT memory immediately after setting a block to bypass causes corruption as bypass only happens at next Vupdate. [HOW] Re-enable mem low power for CM block Force optimization on next flip and disable LUT memory during optimization sequence if LUT select field is then set to bypass v2: squash in CONFIG_DRM_AMD_DC_DCN fix (Alex) Reviewed-by:
Eric Yang <Eric.Yang2@amd.com> Acked-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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- 28 Sep, 2021 23 commits
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Qingqing Zhuo authored
[Why] DC should be used in place of DAL in upstream. [How] Replace dal with dc in function names. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
Qingqing Zhuo <Qingqing.Zhuo@amd.com> Tested-by:
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Aric Cyr authored
This version brings along following fixes: - Fixes to backlight, LUT, PPS, MST - Use correct vpg for 128b/132b encoding - Improved logging for VCP - Replace referral of dal with dc Acked-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
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Anthony Koo authored
Acked-by:
Anthony Koo <Anthony.Koo@amd.com> Tested-by:
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Oliver Logush authored
Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Oliver Logush <oliver.logush@amd.com> Tested-by:
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Ilya authored
[Why] This change is needed for DCN2 to make use of the immediate_update flag. With this flag, update to PPS will be immediate, rather than always taking place on dig_update signal. [How] Set AFMT_GENERIC7_FRAME/IMMEDIATE_UPDATE bits depending on flag value. Reviewed-by:
Ilya <Ilya.Bakoulin@amd.com> Tested-by:
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Jimmy Kizito authored
[Why] MST streams share the same link and should share the same encoder. The current availability check may erroneously determine that an encoder is unavailable for MST streams. [How] When checking for link encoder availability, check if an encoder in use shares a link with the stream for which the availability check is being conducted. If the link is shared, then the link encoder should be shared too and will be deemed available. Reviewed-by:
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Meenakshikumar Somasundaram authored
[Why] Link encoder in the link could be null for certain links. [How] If link encoder in the link is null then get the link encoder from the stream. Reviewed-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Tested-by:
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Wenjing Liu authored
[why] Unify the code which handles the conversion between hw lane setting and dpcd lane setting. v2: squash in unused variable fixes (Alex) Reviewed-by:
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Wenjing Liu authored
[why] To support per lane lane setting adjustment, we need to change cur_lane_setting to an array one for each lane as the first step. Reviewed-by:
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David Galiffi authored
[Why] Requested feature to assist with Thermal, Acoustic, Power, and Performance tuning. [How] Add a debug field that will override calculated minimum DRAM clock, if the debug value is larger than the calculate value. Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
David Galiffi <David.Galiffi@amd.com> Tested-by:
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Eric Yang authored
[Why] To prevent unnecessary wake up of DMCUB when ABM is enabled without PSR enabled, driver will notify DMCUB to stop ABM's vertical interrupts if vsync is disabled and steady state is reached. [How] Send inbox message to notify ABM pause based on vsync on/off Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Michael Strauss authored
[WHY] AFMT is unused for DP audio, so powering it on for DP is unnecessary. [HOW] APG block should be powered down instead, however HW defaults to shutdown state when not enabled so no further work is required. Reviewed-by:
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Anthony Koo authored
Acked-by:
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Wenjing Liu authored
[why] 128b/132b uses the vpg instance assigned to hpo dp stream encoder. The current vpg used is assigned to dio stream encoder. This is incorrect and cause display black screen because the actual vpg is powered off. Reviewed-by:
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Hawking Zhang authored
didn't read the value of mmCP_HQD_QUANTUM from correct register offset Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Le Ma <Le.Ma@amd.com> Signed-off-by:
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Tao Zhou authored
In ras poison mode, umc uncorrectable error will be ignored until the corrupted data consumed by another ras module (such as gfx, sdma). v2: update the debug message and replace dev_warn with dev_info. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
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Tao Zhou authored
Add RAS poison supported flag and tell PSP RAS TA about the info. v2: rename poison mode to poison supported, we can also disable poison mode even we support it. print value of poison supported if ras feature enablement fails. Signed-off-by: -
Tao Zhou authored
Add ras poison mode query interface for UMC. Signed-off-by:
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Tao Zhou authored
Add ras poison mode query interface for DF. v2: replace RREG32_PCIE with RREG32_SOC15. Signed-off-by:
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Candice Li authored
Updated invoke to use new common TA structure similarily to load/unload. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Praful Swarnakar authored
[Why] ASSR is dependent on Signed PSP Verstage to enable Content Protection for eDP panels. Unsigned PSP verstage is used during development phase causing ASSR to FAIL. As a result, link training is performed with DP_PANEL_MODE_DEFAULT instead of DP_PANEL_MODE_EDP for eDP panels that causes display flicker on some panels. [How] - Do not change panel mode, if ASSR is disabled - Just report and continue to perform eDP link training with right settings further. Signed-off-by:
Praful Swarnakar <Praful.Swarnakar@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Leslie Shi authored
gmc_v{9,10}_0_gart_disable() isn't called matched with correspoding gart_enbale function in SRIOV case. This will lead to gart.bo pin_count leak on driver unload. Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:Leslie Shi <Yuliang.Shi@amd.com> Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
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Dave Airlie authored
Merge tag 'amd-drm-next-5.16-2021-09-27' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.16-2021-09-27: amdgpu: - RAS improvements - BACO fixes - Yellow Carp updates - Misc code cleanups - Initial DP 2.0 support - VCN priority handling - Cyan Skillfish updates - Rework IB handling for multimedia engine tests - Backlight fixes - DCN 3.1 power saving improvements - Runtime PM fixes - Modifier support for DCC image stores for gfx 10.3 - Hotplug fixes - Clean up stack related warnings in display code - DP alt mode fixes - Display rework for better handling FP code - Debugfs fixes amdkfd: - SVM fixes - DMA map fixes radeon: - AGP fix From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210927212653.4575-1-alexander.deucher@amd.comSigned-off-by:
Dave Airlie <airlied@redhat.com>
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- 24 Sep, 2021 1 commit
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git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
drm-misc-next for 5.15: UAPI Changes: Cross-subsystem Changes: Core Changes: Driver Changes: - Conversions to dev_err_probe() helper - rockchip: Various build improvements, Use DRM_BRIDGE_ATTACH_NO_CONNECTOR for LVDS and RGB - panel: New panel-edp driver Signed-off-by:
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- 23 Sep, 2021 5 commits
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Alex Deucher authored
It's not used outside of soc15.c Reviewed-by:
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Lijo Lazar authored
Update the current state as boot state during dpm initialization. During the subsequent initialization, set_power_state gets called to transition to the final power state. set_power_state refers to values from the current state and without current state populated, it could result in NULL pointer dereference. For ex: on platforms where PCI speed change is supported through ACPI ATCS method, the link speed of current state needs to be queried before deciding on changing to final power state's link speed. The logic to query ATCS-support was broken on certain platforms. The issue became visible when broken ATCS-support logic got fixed with commit f9b7f370 ("drm/amdgpu/acpi: make ATPX/ATCS structures global (v2)"). Bug:https://gitlab.freedesktop.org/drm/amd/-/issues/1698Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
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Candice Li authored
All code paths under the EAGAIN path in RAS late init are unused. Signed-off-by:
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John Clements authored
Explicity post warning if cmd is issued against unsupported IP Update to latest RAS TA interface Reviewed-by:
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Philip Yang authored
Device manager releases device-specific resources when a driver disconnects from a device, devm_memunmap_pages and devm_release_mem_region calls in svm_migrate_fini are redundant. It causes below warning trace after patch "drm/amdgpu: Split amdgpu_device_fini into early and late", so remove function svm_migrate_fini. BUG: https://gitlab.freedesktop.org/drm/amd/-/issues/1718 WARNING: CPU: 1 PID: 3646 at drivers/base/devres.c:795 devm_release_action+0x51/0x60 Call Trace: ? memunmap_pages+0x360/0x360 svm_migrate_fini+0x2d/0x60 [amdgpu] kgd2kfd_device_exit+0x23/0xa0 [amdgpu] amdgpu_amdkfd_device_fini_sw+0x1d/0x30 [amdgpu] amdgpu_device_fini_sw+0x45/0x290 [amdgpu] amdgpu_driver_release_kms+0x12/0x30 [amdgpu] drm_dev_release+0x20/0x40 [drm] release_nodes+0x196/0x1e0 device_release_driver_internal+0x104/0x1d0 driver_detach+0x47/0x90 bus_remove_driver+0x7a/0xd0 pci_unregister_driver+0x3d/0x90 amdgpu_exit+0x11/0x20 [amdgpu] Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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