- 06 Dec, 2022 12 commits
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Nicholas Kazlauskas authored
[Why] It's currently tied to Z10 support, and is required for Z10, but we can still support Z10 display off without PSR. We currently need to skip the PSR CRTC disable to prevent stuttering and underflow from occuring during PSR-SU. [How] Add a debug option to allow specifying this separately. Reviewed-by:
Robin Chen <robin.chen@amd.com> Acked-by:
Stylon Wang <stylon.wang@amd.com> Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Zhongwei authored
[Why] The input UrgentLatency in CalculateUrgentBurstFactor of prefect check is wrong. [How] Correct to the correct one to keep same as HW formula Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Zhongwei <Zhongwei.Zhang@amd.com> Tested-by:
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Charlene Liu authored
[why] HW register bit define changed. Reviewed-by:
Zhan Liu <Zhan.Liu@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Alvin Lee authored
[Description] - Ensure dc_commit_streams returns the correct return code so any failures can be handled properly in DM layer - If set timings fail and we have to remove MPO planes, do so unconditionally but make sure to mark for removal so we report the VSYNC and prevent timeout - Failure to remove MPO plane results in set timings failure due to lack of resources Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
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Paul Hsieh authored
[Why] There is no DDC_6 pin on new asic cause the mapping table is incorrect. When app try to access DDC_VGA port, driver read an invalid ddc pin status and report engine busy. [How] Add dummy DDC_6 pin to align gpio structure. Reviewed-by:
Paul Hsieh <Paul.Hsieh@amd.com> Tested-by:
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Dillon Varone authored
[Description] If validating for max voltage level (therefore max clocks) always pass over the DET swath fill latency hiding check. Reviewed-by:
Dillon Varone <Dillon.Varone@amd.com> Tested-by:
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Dillon Varone authored
[Description] When subvp is in use, main pipes should block unintended natural uclk pstate changes to prevent disruption to the state machine. Reviewed-by:
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Michael Strauss authored
[WHY] Low dscclk in high vlevels blocks some DSC modes. [HOW] Update dscclk to 1/3 of dispclk. Reviewed-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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David Galiffi authored
[Why] It is not enabled for DCN3.0.1, 3.0.2, 3.0.3. [How] Add `dc->caps.dp_hdmi21_pcon_support = true` to these DCN versions. Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
David Galiffi <David.Galiffi@amd.com> Tested-by:
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Dmytro Laktyushkin authored
Seamless boot requires VBIOS to select dig matching to link order wise. A significant amount of dal logic makes assumption we are using preferred dig for eDP and if this isn't the case then seamless boot is not supported. Reviewed-by:
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Aurabindo Pillai authored
[Why&How] If the timing generator isnt running, it does not make sense to trigger a sync on the corresponding OTG. Check this condition before starting. Otherwise, this will cause error like: *ERROR* GSL: Timeout on reset trigger! Fixes: dc55b106 ("drm/amd/display: Disable phantom OTG after enable for plane disable") Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Chris Park authored
[Why] DTB DTO is programmed more correctly during link enable. Programming them on CLK update which may arrive frequently and sporadically per flip throws off DTB DTO. [How] Remove DTB DTO programming on clock update. Reviewed-by:
Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by:
Chris Park <Chris.Park@amd.com> Tested-by:
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- 02 Dec, 2022 8 commits
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Alex Deucher authored
Expand the GPUVM documentation to better describe the hardware functionality and use cases it serves. v2: Fixed a couple of spelling mistakes. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Luben Tuikov <luben.tuikov@amd.com> Reviewed-by:
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Alex Deucher authored
Add definitions to clarify GPU virtual memory. v2: clarify the terms a bit more Reviewed-by:
Peter Maucher <bellosilicio@gmail.com> Signed-off-by:
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Prike Liang authored
In the SDMA s0ix save process requires to turn off SDMA ring buffer for avoiding the SDMA in-flight request, otherwise will suffer from SDMA page fault which causes by page request from in-flight SDMA ring accessing at SDMA restore phase. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2248 Cc: stable@vger.kernel.org # 6.0,5.15+ Fixes: f8f4e2a5 ("drm/amdgpu: skipping SDMA hw_init and hw_fini for S0ix.") Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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Jiadong.Zhu authored
Trigger Mid-Command Buffer Preemption according to the priority of the software rings and the hw fence signalling condition. The muxer saves the locations of the indirect buffer frames from the software ring together with the fence sequence number in its fifo queue, and pops out those records when the fences are signalled. The locations are used to resubmit packages in preemption scenarios by coping the chunks from the software ring. v2: Update comment style. v3: Fix conflict caused by previous modifications. v4: Remove unnecessary prints. v5: Fix corner cases for resubmission cases. v6: Refactor functions for resubmission, calling fence_process in irq handler. v7: Solve conflict for removing amdgpu_sw_ring.c. v8: Add time threshold to judge if preemption request is needed. v9: Correct comment spelling. Set fence emit timestamp before rsu assignment. Cc: Christian Koenig <Christian.Koenig@amd.com> Cc: Luben Tuikov <Luben.Tuikov@amd.com> Cc: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Cc: Michel Dänzer <michel@daenzer.net> Signed-off-by:
Jiadong.Zhu <Jiadong.Zhu@amd.com> Acked-by:
Huang Rui <ray.huang@amd.com> Acked-by:
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Jiadong.Zhu authored
1. Modify the unmap_queue package on gfx9. Add trailing fence to track the preemption done. 2. Modify emit_ce_meta emit_de_meta functions for the resumed ibs. v2: Restyle code not to use ternary operator. v3: Modify code format. v4: Enable Mid-Command Buffer Preemption for gfx9 by default. v5: Optimize the flag bit set for emit_fence. v6: Modify log message for preemption timeout. Cc: Christian Koenig <Christian.Koenig@amd.com> Cc: Michel Dänzer <michel@daenzer.net> Cc: Luben Tuikov <Luben.Tuikov@amd.com> Signed-off-by:
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Jiadong.Zhu authored
Set ring functions with software ring callbacks on gfx9. The software ring could be tested by debugfs_test_ib case. v2: Set sw_ring 2 to enable software ring by default. v3: Remove the parameter for software ring enablement. v4: Use amdgpu_ring_init/fini for software rings. v5: Update for code format. Fix conflict. v6: Remove unnecessary checks and enable software ring on gfx9 by default. v7: Use static array for software ring names and priorities. v8: Stop creating software rings if no gfx ring existed. Cc: Christian Koenig <Christian.Koenig@amd.com> Cc: Luben Tuikov <Luben.Tuikov@amd.com> Cc: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Cc: Michel Dänzer <michel@daenzer.net> Cc: Likun Gao <Likun.Gao@amd.com> Signed-off-by:
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Jiadong.Zhu authored
The software ring is created to support priority context while there is only one hardware queue for gfx. Every software ring has its fence driver and could be used as an ordinary ring for the GPU scheduler. Multiple software rings are bound to a real ring with the ring muxer. The packages committed on the software ring are copied to the real ring. v2: Use array to store software ring entry. v3: Remove unnecessary prints. v4: Remove amdgpu_ring_sw_init/fini functions, using gtt for sw ring buffer for later dma copy optimization. v5: Allocate ring entry dynamically in the muxer. v6: Update comments for the ring muxer. v7: Modify for function naming. v8: Combine software ring functions into amdgpu_ring_mux.c v9: Use kernel-doc comment on the get_rptr function. Cc: Christian Koenig <Christian.Koenig@amd.com> Cc: Luben Tuikov <Luben.Tuikov@amd.com> Cc: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Cc: Michel Dänzer <michel@daenzer.net> Signed-off-by:
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Hamza Mahfooz authored
Currently, userspace doesn't have a way to communicate selective updates to displays. So, enable support for FB_DAMAGE_CLIPS for DCN ASICs newer than DCN301, convert DRM damage clips to dc dirty rectangles and fill them into dirty_rects in fill_dc_dirty_rects(). Reviewed-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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- 01 Dec, 2022 9 commits
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Peter Maucher authored
The amdgpu kernel module has supported RDNA for a while, mention that in the module description. v2: Add CDNA as well (Alex) Signed-off-by:
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Peter Maucher authored
Document difference between amdgpu.gartsize and amdgpu.gttsize module parameters, as initially explained by Alex Deucher here: https://lists.freedesktop.org/archives/dri-devel/2022-October/375358.html v2: minor cleanups (Alex) Signed-off-by:
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ye xingchen authored
Replace the open-code with sysfs_emit() to simplify the code. Reviewed-by:
ye xingchen <ye.xingchen@zte.com.cn> Signed-off-by:
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Alex Deucher authored
This fixes DMCU initialization in APU GPU passthrough. The DMCU needs the GPU physical address, not the CPU physical address. This ends up working out on bare metal because we always use the physical address, but doesn't work in passthrough because the addresses are different. Reviewed-by:
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YuBiao Wang authored
Under virtualization guest needs to receive notification from host to perform reset in some cases. Add nv mailbox irq in soc21. Signed-off-by:
YuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Leo Liu authored
So that uses PSP to initialize HW. Fixes: 0c2c02b6 ("drm/amdgpu/vcn: add firmware support for dimgrey_cavefish") Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Tao Zhou authored
Configure related registers. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
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Jack Xiao authored
Enable reg active poll in mes11. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Jack Xiao authored
Update the api def of mes11. Signed-off-by:
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- 29 Nov, 2022 11 commits
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Konstantin Meskhidze authored
This commit fixes logic error in function 'amdgpu_hw_ip_info': - value 'uvd' might be 'vcn'. Signed-off-by:Konstantin Meskhidze <konstantin.meskhidze@huawei.com> Signed-off-by:
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Konstantin Meskhidze authored
This patch fixes potential memory leakage and seg fault in _gpuvm_import_dmabuf() function Fixes: d4ec4bdc ("drm/amdkfd: Allow access for mmapping KFD BOs") Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
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Randy Dunlap authored
Fix documentation build errors for amdgpu: correct the filename. Error: Cannot open file ../drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c Error: Cannot open file ../drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c Error: Cannot open file ../drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c WARNING: kernel-doc '../scripts/kernel-doc -rst -enable-lineno -sphinx-version 5.3.0 -function MMU Notifier ../drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c' failed with return code 1 WARNING: kernel-doc '../scripts/kernel-doc -rst -enable-lineno -sphinx-version 5.3.0 -internal ../drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c' failed with return code 2 Fixes: d9483ecd ("drm/amdgpu: rename the files for HMM handling") Signed-off-by:
Randy Dunlap <rdunlap@infradead.org> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Felix Kuehling <Felix.Kuehling@amd.com> Cc: David Airlie <airlied@gmail.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Jonathan Corbet <corbet@lwn.net> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by:
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Xiongfeng Wang authored
As comment of pci_get_class() says, it returns a pci_device with its refcount increased and decreased the refcount for the input parameter @from if it is not NULL. If we break the loop in amdgpu_atrm_get_bios() with 'pdev' not NULL, we need to call pci_dev_put() to decrease the refcount. Add the missing pci_dev_put() to avoid refcount leak. Fixes: d38ceaf9 ("drm/amdgpu: add core driver (v4)") Signed-off-by:
Xiongfeng Wang <wangxiongfeng2@huawei.com> Signed-off-by:
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Guchun Chen authored
Runtime PM can happen pretty frequently, as these printings may be annoyed, switch to dev_dbg. Suggested-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
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Alvin Lee authored
[Description] - When transitioning FRL / DP2 is not required, we will always request DTBCLK = 0Mhz, but PMFW returns the min freq - This causes us to make DTBCLK requests every time we call optimize after transitioning from FRL to non-FRL - If DTBCLK is not required, request the min instead (then we only need to make 1 extra request at boot time) - Also when programming PIPE_DTO_SRC_SEL, don't programming for DP first, just programming once for the required selection (programming DP on an HDMI connection then switching back causes corruption) Reviewed-by:
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Stylon Wang authored
[Why] Tests need to tell if display is connected via USB4 DPIA link. Currently this is only possible via analyzing dmesg logs. [How] Create a per-connector debugfs entry to report if the link is tunneled via USB4 DPIA. Reviewed-by:
Wayne Lin <Wayne.Lin@amd.com> Acked-by:
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Dillon Varone authored
[Description] Output transfer function must be programmed per pipe as part of a front end update when the plane changes, or output transfer function changes for a given plane. Reviewed-by:
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Dillon Varone authored
[Description] Calculations for determining DCC meta size should be pitch*height*bpp/256. Reviewed-by:
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Dillon Varone authored
[Description] Need to subtract unused section of the viewport when calculating required space in MALL for subvp instead of adding, to prevent over allocation. Reviewed-by:
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Alvin Lee authored
[Description] - When entering into a SubVP config that requires a minimal transition we need to retain phantom pipes and also restore the mall config - This is because the min transition will remove phantom pipes from the context (shallow copy) and not restore it's original state - This is just a workaround, and needs a proper fix Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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