1. 17 Jun, 2019 13 commits
    • Raphael Gault's avatar
      perf tests arm64: Compile tests unconditionally · 010e3e8f
      Raphael Gault authored
      In order to subsequently add more tests for the arm64 architecture we
      compile the tests target for arm64 systematically.
      
      Further explanation provided by Mark Rutland:
      
      Given prior questions regarding this commit, it's probably worth
      spelling things out more explicitly, e.g.
      
        Currently we only build the arm64/tests directory if
        CONFIG_DWARF_UNWIND is selected, which is fine as the only test we
        have is arm64/tests/dwarf-unwind.o.
      
        So that we can add more tests to the test directory, let's
        unconditionally build the directory, but conditionally build
        dwarf-unwind.o depending on CONFIG_DWARF_UNWIND.
      
        There should be no functional change as a result of this patch.
      Signed-off-by: default avatarRaphael Gault <raphael.gault@arm.com>
      Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: linux-arm-kernel@lists.infradead.org
      Link: http://lkml.kernel.org/r/20190611125315.18736-2-raphael.gault@arm.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
      010e3e8f
    • Ingo Molnar's avatar
      Merge tag 'perf-core-for-mingo-5.3-20190611' of... · 3ce5aceb
      Ingo Molnar authored
      Merge tag 'perf-core-for-mingo-5.3-20190611' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core
      
      Pull perf/core improvements and fixes from Arnaldo Carvalho de Melo:
      
      perf record:
      
        Alexey Budankov:
      
        - Allow mixing --user-regs with --call-graph=dwarf, making sure that
          the minimal set of registers for DWARF unwinding is present in the
          set of user registers requested to be present in each sample, while
          warning the user that this may make callchains unreliable if more
          that the minimal set of registers is needed to unwind.
      
        yuzhoujian:
      
        - Add support to collect callchains from kernel or user space only,
          IOW allow setting the perf_event_attr.exclude_callchain_{kernel,user}
          bits from the command line.
      
      perf trace:
      
        Arnaldo Carvalho de Melo:
      
        - Remove x86_64 specific syscall numbers from the augmented_raw_syscalls
          BPF in-kernel collector of augmented raw_syscalls:sys_{enter,exit}
          payloads, use instead the syscall numbers obtainer either by the
          arch specific syscalltbl generators or from audit-libs.
      
        - Allow 'perf trace' to ask for the number of bytes to collect for
          string arguments, for now ask for PATH_MAX, i.e. the whole
          pathnames, which ends up being just a way to speficy which syscall
          args are pathnames and thus should be read using bpf_probe_read_str().
      
        - Skip unknown syscalls when expanding strace like syscall groups.
          This helps using the 'string' group of syscalls to work in arm64,
          where some of the syscalls present in x86_64 that deal with
          strings, for instance 'access', are deprecated and this should not
          be asked for tracing.
      
        Leo Yan:
      
        - Exit when failing to build eBPF program.
      
      perf config:
      
        Arnaldo Carvalho de Melo:
      
        - Bail out when a handler returns failure for a key-value pair. This
          helps with cases where processing a key-value pair is not just a
          matter of setting some tool specific knob, involving, for instance
          building a BPF program to then attach to the list of events 'perf
          trace' will use, e.g. augmented_raw_syscalls.c.
      
      perf.data:
      
        Kan Liang:
      
        - Read and store die ID information available in new Intel processors
          in CPUID.1F in the CPU topology written in the perf.data header.
      
      perf stat:
      
        Kan Liang:
      
        - Support per-die aggregation.
      
      Documentation:
      
        Arnaldo Carvalho de Melo:
      
        - Update perf.data documentation about the CPU_TOPOLOGY, MEM_TOPOLOGY,
          CLOCKID and DIR_FORMAT headers.
      
        Song Liu:
      
        - Add description of headers HEADER_BPF_PROG_INFO and HEADER_BPF_BTF.
      
        Leo Yan:
      
        - Update default value for llvm.clang-bpf-cmd-template in 'man perf-config'.
      
      JVMTI:
      
        Jiri Olsa:
      
        - Address gcc string overflow warning for strncpy()
      
      core:
      
        - Remove superfluous nthreads system_wide setup in perf_evsel__alloc_fd().
      
      Intel PT:
      
        Adrian Hunter:
      
        - Add support for samples to contain IPC ratio, collecting cycles
          information from CYC packets, showing the IPC info periodically, because
          Intel PT does not update the cycle count on every branch or instruction,
          the incremental values will often be zero.  When there are values, they
          will be the number of instructions and number of cycles since the last
          update, and thus represent the average IPC since the last IPC value.
      
          E.g.:
      
          # perf record --cpu 1 -m200000 -a -e intel_pt/cyc/u sleep 0.0001
          rounding mmap pages size to 1024M (262144 pages)
          [ perf record: Woken up 0 times to write data ]
          [ perf record: Captured and wrote 2.208 MB perf.data ]
          # perf script --insn-trace --xed -F+ipc,-dso,-cpu,-tid
          #
          <SNIP + add line numbering to make sense of IPC counts e.g.: (18/3)>
          1   cc1 63501.650479626: 7f5219ac27bf _int_free+0x3f   jnz 0x7f5219ac2af0       IPC: 0.81 (36/44)
          2   cc1 63501.650479626: 7f5219ac27c5 _int_free+0x45   cmp $0x1f, %rbp
          3   cc1 63501.650479626: 7f5219ac27c9 _int_free+0x49   jbe 0x7f5219ac2b00
          4   cc1 63501.650479626: 7f5219ac27cf _int_free+0x4f   test $0x8, %al
          5   cc1 63501.650479626: 7f5219ac27d1 _int_free+0x51   jnz 0x7f5219ac2b00
          6   cc1 63501.650479626: 7f5219ac27d7 _int_free+0x57   movq  0x13c58a(%rip), %rcx
          7   cc1 63501.650479626: 7f5219ac27de _int_free+0x5e   mov %rdi, %r12
          8   cc1 63501.650479626: 7f5219ac27e1 _int_free+0x61   movq  %fs:(%rcx), %rax
          9   cc1 63501.650479626: 7f5219ac27e5 _int_free+0x65   test %rax, %rax
         10   cc1 63501.650479626: 7f5219ac27e8 _int_free+0x68   jz 0x7f5219ac2821
         11   cc1 63501.650479626: 7f5219ac27ea _int_free+0x6a   leaq  -0x11(%rbp), %rdi
         12   cc1 63501.650479626: 7f5219ac27ee _int_free+0x6e   mov %rdi, %rsi
         13   cc1 63501.650479626: 7f5219ac27f1 _int_free+0x71   shr $0x4, %rsi
         14   cc1 63501.650479626: 7f5219ac27f5 _int_free+0x75   cmpq  %rsi, 0x13caf4(%rip)
         15   cc1 63501.650479626: 7f5219ac27fc _int_free+0x7c   jbe 0x7f5219ac2821
         16   cc1 63501.650479626: 7f5219ac2821 _int_free+0xa1   cmpq  0x13f138(%rip), %rbp
         17   cc1 63501.650479626: 7f5219ac2828 _int_free+0xa8   jnbe 0x7f5219ac28d8
         18   cc1 63501.650479626: 7f5219ac28d8 _int_free+0x158  testb  $0x2, 0x8(%rbx)
         19   cc1 63501.650479628: 7f5219ac28dc _int_free+0x15c  jnz 0x7f5219ac2ab0       IPC: 6.00 (18/3)
          <SNIP>
      
        - Allow using time ranges with Intel PT, i.e. these features, already
          present but not optimially usable with Intel PT, should be now:
      
              Select the second 10% time slice:
      
              $ perf script --time 10%/2
      
              Select from 0% to 10% time slice:
      
              $ perf script --time 0%-10%
      
              Select the first and second 10% time slices:
      
              $ perf script --time 10%/1,10%/2
      
              Select from 0% to 10% and 30% to 40% slices:
      
              $ perf script --time 0%-10%,30%-40%
      
      cs-etm (ARM):
      
        Mathieu Poirier:
      
        - Add support for CPU-wide trace scenarios.
      
      s390:
      
        Thomas Richter:
      
        - Fix missing kvm module load for s390.
      
        - Fix OOM error in TUI mode on s390
      
        - Support s390 diag event display when doing analysis on !s390
          architectures.
      Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
      Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
      3ce5aceb
    • Jiri Olsa's avatar
      perf/x86/intel: Disable check_msr for real HW · d0e1a507
      Jiri Olsa authored
      Tom Vaden reported false failure of the check_msr() function, because
      some servers can do POST tracing and enable LBR tracing during
      bootup.
      
      Kan confirmed that check_msr patch was to fix a bug report in
      guest, so it's ok to disable it for real HW.
      Reported-by: default avatarTom Vaden <tom.vaden@hpe.com>
      Signed-off-by: default avatarJiri Olsa <jolsa@kernel.org>
      Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
      Acked-by: default avatarTom Vaden <tom.vaden@hpe.com>
      Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
      Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
      Cc: Liang Kan <kan.liang@linux.intel.com>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Namhyung Kim <namhyung@kernel.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Link: https://lkml.kernel.org/r/20190616141313.GD2500@krava
      [ Readability edits. ]
      Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
      d0e1a507
    • Jiri Olsa's avatar
      perf/x86/intel: Use ->is_visible callback for default group · b7c9b392
      Jiri Olsa authored
      It's preffered to use group's ->is_visible callback, so
      we do not need to use condition attribute assignment.
      Suggested-by: default avatarPeter Zijlstra <peterz@infradead.org>
      Signed-off-by: default avatarJiri Olsa <jolsa@kernel.org>
      Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
      Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
      Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Namhyung Kim <namhyung@kernel.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Link: https://lkml.kernel.org/r/20190524132152.GB26617@kravaSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
      b7c9b392
    • Kan Liang's avatar
      perf/x86/intel/uncore: Add IMC uncore support for Snow Ridge · ee49532b
      Kan Liang authored
      IMC uncore unit can only be accessed via MMIO on Snow Ridge.
      The MMIO space of IMC uncore is at the specified offsets from the
      MEM0_BAR. Add snr_uncore_get_mc_dev() to locate the PCI device with
      MMIO_BASE and MEM0_BAR register.
      
      Add new ops to access the IMC registers via MMIO.
      
      Add 3 new free running counters for clocks, read and write bandwidth.
      Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
      Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: acme@kernel.org
      Cc: eranian@google.com
      Link: https://lkml.kernel.org/r/1556672028-119221-7-git-send-email-kan.liang@linux.intel.comSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
      ee49532b
    • Kan Liang's avatar
      perf/x86/intel/uncore: Clean up client IMC · 07ce734d
      Kan Liang authored
      The client IMC block is accessed by MMIO. Current code uses an informal
      way to access the block, which is not recommended.
      
      Clean up the code by using __iomem annotation and the accessor
      functions (read[lq]()).
      
      Move exit_box() and read_counter() to generic code, which can be shared
      with the server code later.
      Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
      Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: acme@kernel.org
      Cc: eranian@google.com
      Link: https://lkml.kernel.org/r/1556672028-119221-6-git-send-email-kan.liang@linux.intel.comSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
      07ce734d
    • Kan Liang's avatar
      perf/x86/intel/uncore: Support MMIO type uncore blocks · 3da04b8a
      Kan Liang authored
      A new MMIO type uncore box is introduced on Snow Ridge server. The
      counters of MMIO type uncore box can only be accessed by MMIO.
      
      Add a new uncore type, uncore_mmio_uncores, for MMIO type uncore blocks.
      
      Support MMIO type uncore blocks in CPU hot plug. The MMIO space has to
      be map/unmap for the first/last CPU. The context also need to be
      migrated if the bind CPU changes.
      
      Add mmio_init() to init and register PMUs for MMIO type uncore blocks.
      
      Add a helper to calculate the box_ctl address.
      
      The helpers which calculate ctl/ctr can be shared with PCI type uncore
      blocks.
      Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
      Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: acme@kernel.org
      Cc: eranian@google.com
      Link: https://lkml.kernel.org/r/1556672028-119221-5-git-send-email-kan.liang@linux.intel.comSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
      3da04b8a
    • Kan Liang's avatar
      perf/x86/intel/uncore: Factor out box ref/unref functions · c8872d90
      Kan Liang authored
      For uncore box which can only be accessed by MSR, its reference
      box->refcnt is updated in CPU hot plug. The uncore boxes need to be
      initalized and exited accordingly for the first/last CPU of a socket.
      
      Starts from Snow Ridge server, a new type of uncore box is introduced,
      which can only be accessed by MMIO. The driver needs to map/unmap
      MMIO space for the first/last CPU of a socket.
      
      Extract the codes of box ref/unref and init/exit for reuse later.
      
      There is no functional change.
      Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
      Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: acme@kernel.org
      Cc: eranian@google.com
      Link: https://lkml.kernel.org/r/1556672028-119221-4-git-send-email-kan.liang@linux.intel.comSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
      c8872d90
    • Kan Liang's avatar
      perf/x86/intel/uncore: Add uncore support for Snow Ridge server · 210cc5f9
      Kan Liang authored
      The uncore subsystem on Snow Ridge is similar as previous SKX server.
      The uncore units on Snow Ridge include Ubox, Chabox, IIO, IRP, M2PCIE,
      PCU, M2M, PCIE3 and IMC.
      
      - The config register encoding and pci device IDs are changed.
      - For CHA, the umask_ext and filter_tid fields are changed.
      - For IIO, the ch_mask and fc_mask fields are changed.
      - For M2M, the mask_ext field is changed.
      - Add new PCIe3 unit for PCIe3 root port which provides the interface
        between PCIe devices, plugged into the PCIe port, and the components
        (in M2IOSF).
      - IMC can only be accessed via MMIO on Snow Ridge now. Current common
        code doesn't support it yet. IMC will be supported in following
        patches.
      - There are 9 free running counters for IIO CLOCKS and bandwidth In.
      - Full uncore event list is not published yet. Event constrain is not
        included in this patch. It will be added later separately.
      Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
      Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: acme@kernel.org
      Cc: eranian@google.com
      Link: https://lkml.kernel.org/r/1556672028-119221-3-git-send-email-kan.liang@linux.intel.comSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
      210cc5f9
    • Kan Liang's avatar
      perf/x86/intel/uncore: Handle invalid event coding for free-running counter · 543ac280
      Kan Liang authored
      Counting with invalid event coding for free-running counter may cause
      OOPs, e.g. uncore_iio_free_running_0/event=1/.
      
      Current code only validate the event with free-running event format,
      event=0xff,umask=0xXY. Non-free-running event format never be checked
      for the PMU with free-running counters.
      
      Add generic hw_config() to check and reject the invalid event coding
      for free-running PMU.
      Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
      Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: acme@kernel.org
      Cc: eranian@google.com
      Fixes: 0f519f03 ("perf/x86/intel/uncore: Support IIO free-running counters on SKX")
      Link: https://lkml.kernel.org/r/1556672028-119221-2-git-send-email-kan.liang@linux.intel.comSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
      543ac280
    • Kan Liang's avatar
      perf/x86/intel: Add more Icelake CPUIDs · faaeff98
      Kan Liang authored
      Add new model number for Icelake desktop and server to perf.
      
      The data source encoding for Icelake server is the same as Skylake
      server.
      Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
      Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: bp@alien8.de
      Cc: qiuxu.zhuo@intel.com
      Cc: rui.zhang@intel.com
      Cc: tony.luck@intel.com
      Link: https://lkml.kernel.org/r/20190603134122.13853-2-kan.liang@linux.intel.comSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
      faaeff98
    • Kan Liang's avatar
      perf/x86/intel: Add Icelake desktop CPUID · 2a538fda
      Kan Liang authored
      Add new Icelake desktop CPUID for RAPL, CSTATE and UNCORE.
      Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
      Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: bp@alien8.de
      Cc: qiuxu.zhuo@intel.com
      Cc: rui.zhang@intel.com
      Cc: tony.luck@intel.com
      Link: https://lkml.kernel.org/r/20190603134122.13853-3-kan.liang@linux.intel.comSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
      2a538fda
    • Ingo Molnar's avatar
  2. 14 Jun, 2019 2 commits
  3. 13 Jun, 2019 1 commit
  4. 10 Jun, 2019 24 commits