- 14 Jun, 2024 40 commits
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Anthony Koo authored
- Change ordering of structs to put enums together - Add new define DMUB_TRACE_ENTRY_DEFINED to guard the trace code enum Acked-by:
Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Nicholas Kazlauskas authored
[Why] Adds support for performing the sequential ONO changes from DCN351 into DCN35 ASIC based on revision. [How] Check the revision and run the DCN351 sequences on applicable revisions. Reviewed-by:
Sung joon Kim <sungjoon.kim@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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Alvin Lee authored
[Description] Phantom DTBCLK can be calculated different from main because phantom has no DSC and thus will have a different output BPP. Ignore phantom DTBCLK requirement and only consider non-phantom DTBCLK requirements. Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Acked-by:
Alvin Lee <alvin.lee2@amd.com> Tested-by:
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Michael Strauss authored
[WHY] Some sinks are observed to return invalid LTTPR revision and/or invalid LTTPR link rate capabilities. [HOW] Assume any LTTPR which reports invalid max link rate supports HBR3. Don't validate LTTPR DPCD revision in dp_is_lttpr_present check. Reviewed-by:
George Shen <george.shen@amd.com> Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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Michael Strauss authored
[WHY] Needed for PHY patterns as well to perform electrical compliance. Also need to increase wait time from 30ms to 50ms to resolve very intermittent UHBR20 link training failures. Reviewed-by:
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Wenjing Liu authored
[why] We need to decrease ODM slice when adding or removing planes because MPO support takes precedence over dynamic ODM combine. However there is a case where we remove ODM combine even for ODM combine required timing in the initial new dc state. This is normally okay because ODM will be added back after we pass DML bandwidth validation. However since we remove ODM combine in the initial new state, the previous ODM pipe allocation is lost. This may cause the new plane to take away the original secondary OPP head pipe that is still required in the new state. For a timing that requires ODM 2:1 but optimized with ODM 4:1, if we add an MPO plane, we will not have enough pipe to preserve ODM 4:1. In this case we should reduce ODM slice count then try to add the MPO plane again. By reducing, we are gradually remove 1 ODM slice from right most side one at a time until we have enough free pipes for the new plane. If we remove ODM combine entirely, we could use the pipe at ODM slice index 1 as a DPP pipe for the new plane. But ODM slice 1 is still needed as the timing requires ODM 2:1. This transition is not seamless and user will see corruption on the screen. [how] Remove single ODM slice one at time until we have enough pipes for a new plane. Remove previous logic to always remove ODM combine entirely. Reviewed-by:
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Nevenko Stupar authored
[Why & How] Remove some cursor offset calculations for rotated cursor for fixing a bug where multiple cursors are seen. Reviewed-by:
Nevenko Stupar <nevenko.stupar@amd.com> Tested-by:
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Daniel Sa authored
why: DML21 being overwritten after init. how: After initializing, early return. Reviewed-by:
Daniel Sa <daniel.sa@amd.com> Tested-by:
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Chris Park authored
[Why] Official Release CTA specification reverted the change and no longer uses version 5 to indicate OVT timing. [How] Change the version used for AVI info Frame for OVT to 4. Reviewed-by:
Leo Ma <hanghong.ma@amd.com> Acked-by:
Chris Park <chris.park@amd.com> Tested-by:
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Alvin Lee authored
[Description] No need to assign stream_status NULL because it is always re-assigned before usage. This change is to fix coverity errors. Reviewed-by:
Nicholas Choi <nicholas.choi@amd.com> Acked-by:
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Zaeem Mohamed authored
[WHY] Duplicate headers requiring unecessary maintenance of both headers [HOW] Removal of smu13_driver_if header and all referneces to it changed to dcn32_smu13_driver Signed-off-by:
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Ivan Lipski authored
[WHY] Coverity analysis flagged this ternary operation as DEADCODE. Since 'total_y_free_entry' is initialized as 0x200 and 'total_c_free_entry' is initialized as 0x140, and they never change values before the ternary operator, so 'total_y_free_entry' is always greater 'total_c_free_entry', 'so small_free_entry' is always set to 'total_c_free_entry'. [HOW] Replace the ternary operator with the variable declaration. Signed-off-by:
Ivan Lipski <ivlipski@amd.com> Acked-by:
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Ivan Lipski authored
[WHY] Coverity analysis flagged this code as DEADCODE since the condition and return in the outer loop are never reached. All operations with the 'dwb_pipe' variable happen in the inner loop, that already contains the same check with the 'MAX_DWB_PIPES'. The later check condition cannot occur before the check condition in the inner loop, thus the later condition is unreacable. [HOW] Remove the unreachable condition. Acked-by:
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Ivan Lipski authored
[WHY] Coverity analysis flagged the two if conditions in dcn30_dpp.c and dcn401_dpp.c as DEADCODE since they are never true, since the variable 'program_prealpha_dealpha' is initialized at 0 and never chagnes. [HOW] Removed the variable 'program_prealpha_dealpha' and the if conditions. Acked-by:
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Wenjing Liu authored
[why] OPP input rect aka odm slice rect is a hardware dependent parameter that can't be determined by SPL software logic. Therefore we need to explicitly pass odm slice rect in. So ODM slice rect calculation is moved out of SPL. [how] add odm_slice_rect parameter in spl_in Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] When optc uses two pixel per container, each ODM slice width must be an even number. [how] If ODM slice width is odd number increase it by 1. Reviewed-by:
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Dennis Chan authored
When PHY power off, the DP_SEC_CNTL cannot be configured and cause disable Adaptive sync SDP failed. Regarding the issue, the driver will disabled AS-SDP in replay state machine. Reviewed-by:
Dennis Chan <dennis.chan@amd.com> Tested-by:
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ChunTao Tso authored
[Why] Because ABM will wait VStart to start getting histogram data, it will cause we can't enter IPS while full screnn video playing. [How] Modify the panel refresh rate to the maximun multiple of current refresh rate Reviewed-by:
ChunTao Tso <ChunTao.Tso@amd.com> Tested-by:
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Leon Huang authored
[Why] Dmub provides several Replay residency calculation methods, but current interface only supports either ALPM or PHY mode [How] Modify the interface for supporting different types of Replay residency calculation. Reviewed-by:
Leon Huang <Leon.Huang1@amd.com> Tested-by:
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ChunTao Tso authored
[Why] The original coasting vtotal is 2 bytes, and it need to be amended to 4 bytes because low hz case. [How] Amend coasting vtotal from 2 bytes to 4 bytes. Reviewed-by:
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pochchan authored
For some specific panel, it need to use TPS3 rather than use TP2 in ALPM when DSC is enabled. Reviewed-by:
pochchan <pochchan@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] We can hang in place trying to send commands when the DMCUB isn't powered on. [How] For functions that execute within a DC context or DC lock we can wrap the direct calls to dm_execute_dmub_cmd/list with code that exits idle power optimizations and reallows once we're done with the command submission on success. For DM direct submissions the DM will need to manage the enter/exit sequencing manually. We cannot invoke a DMCUB command directly within the DM execution helper or we can deadlock. Reviewed-by:
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Nicholas Kazlauskas authored
[Why] These functions can be called from high IRQ levels and the OS will hang if it tries to use a usleep_highres or a msleep. [How] Replace the flseep with a udelay for dmub_replay_enable. Reviewed-by:
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Christian König authored
This reverts commit b8c415e3 ("drm/amdgpu: take runtime pm reference when we attach a buffer") and commit 425285d3 ("drm/amdgpu: add amdgpu runpm usage trace for separate funcs"). Taking a runtime pm reference for DMA-buf is actually completely unnecessary and even dangerous. The problem is that calling pm_runtime_get_sync() from the DMA-buf callbacks is illegal because we have the reservation locked here which is also taken during resume. So this would deadlock. When the buffer is in GTT it is still accessible even when the GPU is powered down and when it is in VRAM the buffer gets migrated to GTT before powering down. The only use case which would make it mandatory to keep the runtime pm reference would be if we pin the buffer into VRAM, and that's not something we currently do. v2: improve the commit message Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Rodrigo Siqueira authored
Use dc_wake_and_execute_gpint with DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY to get the replay state. Signed-off-by:
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Yang Wang authored
refine imu firmware loading Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
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Yang Wang authored
refine pmfw/smu firmware loading Signed-off-by:
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Yang Wang authored
refine gmc firmware loading Signed-off-by:
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Yang Wang authored
refine vpe firmware loading Signed-off-by:
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Yang Wang authored
refine vcn firmware loading Signed-off-by:
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Yang Wang authored
adjust the function position to better match aca/mca fini code in ras_fini(). Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Bob Zhou authored
To fix potential overflowed constant warning, modify the variables to u32 for getting the return value of RREG32_SOC15(). Signed-off-by:
Bob Zhou <bob.zhou@amd.com> Acked-by:
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Harish Kasiviswanathan authored
To achieve full occupancy CP hardware needs to know if CUs in SE are symmetrically or asymmetrically harvested v2: Reset is_symmetric_cus for each loop Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Acked-by:
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Lijo Lazar authored
Skip scheduling coredump when gpu reset is intentionally triggered through debugfs. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Asad Kamal <asad.kamal@amd.com> Reviewed-by:
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Yang Wang authored
refine sdma firmware loading Signed-off-by:
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Yang Wang authored
refine psp firmware loading Signed-off-by:
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Yunxiang Li authored
We need to take the reset domain lock before talking to MES. While in this case we can take the lock inside the mes helper. We can't do so for most other mes helpers since they are used during reset. So for consistency sake we add the lock here. Signed-off-by:
Yunxiang Li <Yunxiang.Li@amd.com> Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
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Yang Wang authored
v1: refine mes firmware loading v2: use dev_info instead of DRM_INFO Signed-off-by:
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Mukul Joshi authored
Add missing locking at a few places when calling MES APIs to ensure exclusive access to MES queue. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
Kent Russell <kent.russell@amd.com> Signed-off-by:
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Mario Limonciello authored
Currently, amdgpu will always set up the brightness at 100% when it loads. However this is jarring when the BIOS has it previously programmed to a much lower value. The ACPI ATIF method includes two members for "ac_level" and "dc_level". These represent the default values that should be used if the system is brought up in AC and DC respectively. Use these values to set up the default brightness when the backlight device is registered. v2: squash in ACPI fix Reviewed-by:
Leo Li <sunpeng.li@amd.com> Acked-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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