- 02 Feb, 2019 1 commit
-
-
Jeffrey Hugo authored
Add nodes for USB and related PHYs. Signed-off-by:
Jeffrey Hugo <jhugo@codeaurora.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
Andy Gross <andy.gross@linaro.org>
-
- 25 Jan, 2019 25 commits
-
-
Bjorn Andersson authored
Define all six QUP controllers, both as SPI and I2C, allowing boards to enable these as needed. Associated pinmux states are also defined, to require only pinconf states to be specified by the boards, as they are enabled. Note that SPI has not been tested. Reviewed-by:
Vinod Koul <vkoul@kernel.org> Signed-off-by:
-
Bjorn Andersson authored
Add the BLSP2 BAM and add the remaining four UARTs found on the QCS404 platform. Note that these has not been tested. Reviewed-by:
-
Bjorn Andersson authored
BLSP1 UART2 is used as debug uart on the EVB development board, define pinmux state for the UART in the platform dtsi and pinconf state for it in the board dts. Reviewed-by:
-
Bjorn Andersson authored
Fix up the lpasscc address and size, missed during the conversion to address- and size-cells of 2. Reviewed-by:
Douglas Anderson <dianders@chromium.org> Reported-by:
-
Sai Prakash Ranjan authored
Remove the duplicate inclusion of qcom,gcc-sdm845.h mistakenly introduced by commit 6e17f814 ("arm64: dts: sdm845: add prng-ee node"). Reviewed-by:
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> [bjorn: Also fix sort order of lpasscc include, while we're there] Signed-off-by:
-
Sibi Sankar authored
Add reserve-memory nodes for mpss and mba required for remoteproc mss pil. Reviewed-by:
Sibi Sankar <sibis@codeaurora.org> Signed-off-by:
-
Evan Green authored
Add the gpio-ranges property to the TLMM node so that GPIO hogs work. Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
Evan Green <evgreen@chromium.org> Signed-off-by:
-
Bjorn Andersson authored
For devices attached to an IOMMU, translation between IOVA and physical addresses is no longer 1:1 and dma-ranges should be specified to describe the available IOVA address space. On SDM845 the busses are implemented with 36 address bits, so dma-ranges must be defined to reduce the size of the IOVA address space from the 48 bits supported by the SMMU. Without this DMA allocations may end up with IOVAs outside the valid range, that gets truncated by the bus between the device and its translation unit. Also extend ranges to describe the available address space. Tested-by:
-
Bjorn Andersson authored
The busses on SDM845 provides 36 address bits, extend the address and size cells to make it possible to describe this in "ranges" and "dma-ranges". While touching all reg properties, addresses are padded to 8 digits. Tested-by:
-
Rajendra Nayak authored
Add the DT node for the rpmhpd powercontroller. Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by:
Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by:
-
Rajendra Nayak authored
Add rpmpd device node and its OPP table Reviewed-by:
Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by:
-
Govind Singh authored
Add device node for the ath10k SNOC platform driver probe and add resources required for WCN3990 on SDM845 soc. Reviewed-by:
Brian Norris <briannorris@chromium.org> Tested-by:
Govind Singh <govinds@codeaurora.org> Signed-off-by:
-
Sibi Sankar authored
This patch adds the node to support PDC Global reset driver on SDM845 SoCs Reviewed-by:
-
Sibi Sankar authored
Add SCM DT node to enable SCM functionality on SDM845. Reviewed-by:
-
Manu Gautam authored
Correct address for pcs_misc register region of USB3 QMP UNI PHY. These registers are used during runtime-suspend/resume routines of phy. Reviewed-by:
Manu Gautam <mgautam@codeaurora.org> Signed-off-by:
-
Taniya Das authored
This adds the low pass audio clock controller node to sdm845 based on the example in the bindings. Reviewed-by:
Taniya Das <tdas@codeaurora.org> [bjorn: Disabled lpasscc node, as it's normally protected] Signed-off-by:
-
Taniya Das authored
This adds the video clock controller node to sdm845 based on the examples in the bindings. Signed-off-by:
-
Douglas Anderson authored
Add the GPU clock controller nodes as per the example. Signed-off-by:
-
Douglas Anderson authored
This adds the Quad SPI controller to the main sdm845 device tree file. Boards will be expected to assign the proper pinctrl depending on how many chip selects they have hooked up and how many data lines. This depends on commit 48735597 ("clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header") to add the needed defines. It also shouldn't land until the patch ("dt-bindings: spi: Qualcomm Quad SPI(QSPI) documentation") [1] lands. [1] https://lkml.kernel.org/r/20181002214709.162330-1-ryandcase@chromium.orgReviewed-by:
-
Jeffrey Hugo authored
msm8998 has a dozen i2c controllers which can be used to connect to board specific peripherals. Enumerate the controllers so that boards can wire up as needed. Signed-off-by:
-
Jeffrey Hugo authored
l21 is used as sdcard vmmc, and needs the load increased to prevent voltage drop issues with some sdcards. This addresses -84 errors seen during sdcard init with SDR104 cards. Signed-off-by:
-
Andy Gross authored
-
Andy Gross authored
Qualcomm ARM64 Fixes for 5.0-rc3 * Fix irq controller compatible for the MSM8996 platforms
-
Jeykumar Sankaran authored
DPU is short for the Display Processing Unit. It is the display controller on Qualcomm SDM845 chips. This change adds MDSS and DSI nodes to enable display on the target device. Changes in v2: - Beefed up commit message - Use SoC specific compatibles for mdss and dpu (Rob H) - Use assigned-clocks to set initial clock frequency(Rob H) Changes in v3: - added IOMMU node - Fix device naming (remove _phys) - Use correct IRQ_TYPE in interrupt specifiers Changes in v4: - move mdss node to preserve the unit address sort order - remove _clk suffix from dsi clocks (both the comments are from Doug Anderson) Changes in v5: - Keep the device status "disabled" by default (Bjorn Andersson) - Use MDSS_GDSC macro (Jordan) - Fix phy-names (Jordan) - List reg ranges in numerical order (Jordan) Changes in v6: - Separating this patch out of the series - fix phy-names Signed-off-by:
Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by:
Sean Paul <seanpaul@chromium.org> Reviewed-by:
-
Srinivas Kandagatla authored
Add compatible to gicv3 node to enable quirk required to restrict writing to GICR_WAKER register which is restricted on msm8996 SoC in Hypervisor. With this quirk MSM8996 can at least boot out of mainline, which can help community to work with boards based on MSM8996. Without this patch Qualcomm DB820c board reboots on mainline. Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by:
-
- 14 Jan, 2019 13 commits
-
-
Loic Poulain authored
Add watchdog child node to the PM8916 PON device. Signed-off-by:
Loic Poulain <loic.poulain@linaro.org> Signed-off-by:
-
Jakob Wuhrer authored
gpiio5 is missspelt in msm8996-pins.dtsi, fix that. Signed-off-by:
Jakob Wuhrer <jakobwuhrer@airmail.cc> Signed-off-by:
-
Loic Poulain authored
In the same way as for msm8974-hammerhead, l11 load, used for SDCARD VMMC, needs to be increased in order to prevent any voltage drop issues (due to limited current) happening with some SDCARDS or during specific operations (e.g. write). Tested on Dragonboard-410c and DART-SD410 boards. Fixes: 4c7d53d1 (arm64: dts: apq8016-sbc: add regulators support) Reported-by:
Manabu Igusa <migusa@arrowjapan.com> Signed-off-by:
-
Amit Kucheria authored
The PMS405 PMIC has an ADC that exposes the on-die temperature that we wire up to spmi-temp-alarm thermal driver. This allows the PMIC temperature to be exposed to Linux through the thermal framework. Signed-off-by:
Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by:
-
Govind Singh authored
Add device node for the ath10k SNOC platform driver probe and add resources required for WCN3990 on qcs404 soc. Optional clock and regulator controls are not yet available in upstream, hence add them once available. Reviewed-by:
-
Jorge Ramirez-Ortiz authored
The controller can support EXT_CSD_CARD_TYPE_HS400_1_8V cards. Signed-off-by:
Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by:
-
Taniya Das authored
This change adds the cpufreq node as per the bindings example for SDM845. Reviewed-by:
Matthias Kaehlcke <mka@chromium.org> Signed-off-by:
-
Evan Green authored
Add the second lane registers for the USB PHY, now that the QMP phy bindings have been updated. This way the driver can stop reaching beyond its register region to get at the second lane. Reviewed-by:
-
Can Guo authored
Enable the UFS host controller and PHY on sdm845-mtp. Reviewed-by:
Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by:
Can Guo <cang@codeaurora.org> Signed-off-by:
-
Evan Green authored
Add the UFS controller and PHY to SDM845. Reviewed-by:
-
Vivek Gautam authored
Add device node for arm,mmu-500 available on sdm845. This MMU-500 with single TCU and multiple TBU architecture is shared among all the peripherals except gpu. Signed-off-by:
-
Evan Green authored
Enable support for one of the micro SD slots on the MTP. Reviewed-by:
-
Evan Green authored
Add one of the two SD controllers to SDM845. Reviewed-by:
-
- 07 Jan, 2019 1 commit
-
-
Linus Torvalds authored
-
