- 25 Sep, 2018 40 commits
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Nadav Amit authored
As we want to leave as little as possible on the global balloon structure, to avoid possible future races, we want to get rid sysinfo. We can actually get the total_ram directly, and simplify the logic of vmballoon_send_get_target() a little. While we are doing that, let's return int and avoid mistakes due to bool/int conversions. Reviewed-by:
Xavier Deguillard <xdeguillard@vmware.com> Signed-off-by:
Nadav Amit <namit@vmware.com> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Nadav Amit authored
The required change in the balloon size is currently computed in vmballoon_work(), vmballoon_inflate() and vmballoon_deflate(). Refactor it to simplify the next patches. Reviewed-by:
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Nadav Amit authored
The name of the macro'd VMW_BALLOON_2M_SHIFT is misleading. The value reflects 2M huge-page order. Unfortunately, we cannot use HPAGE_PMD_ORDER, since it is not defined when transparent huge-pages are off, so we need to define our own one. Rename it to VMW_BALLOON_2M_ORDER. No functional change. Signed-off-by:
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Nadav Amit authored
Currently, when the hypervisor rejects a page during lock operation, the VM treats pages differently according to the error-code: in certain cases the page is immediately freed, and in others it is put on a rejection list and only freed later. The behavior does not make too much sense. If the page is freed immediately it is very likely to be used again in the next batch of allocations, and be rejected again. In addition, for support of compaction and OOM notifiers, we wish to separate the logic that communicates with the hypervisor (as well as analyzes the status of each page) from the logic that allocates or free pages. Treat all errors the same way, queuing the pages on the refuse list. Move to the next allocation size (4k) when too many pages are refused. Free the refused pages when moving to the next size to avoid situations in which too much memory is waiting to be freed on the refused list. Reviewed-by:
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Nadav Amit authored
The current abstractions for batch vs single operations seem suboptimal and complicate the implementation of additional features (OOM, compaction). The immediate problem of the current abstractions is that they cause differences in how operations are handled when batching is on or off. For example, the refused_alloc counter is not updated when batching is on. These discrepancies are caused by code redundancies. Instead, this patch presents three type of operations, according to whether batching is on or off: (1) add page, (2) communication with the hypervisor and (3) retrieving the status of a page. To avoid the overhead of virtual functions, and since we do not expect additional interfaces for communication with the hypervisor, we use static keys instead of virtual functions. Finally, while we are at it, change vmballoon_init_batching() to return int instead of bool, to be consistent in the return type and avoid potential coding errors. Reviewed-by:
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Nadav Amit authored
Splitting the allocations between sleeping and non-sleeping made some sort of sense as long as rate-limiting was enabled. Now that it is removed, we need to decide - either we want sleeping allocations or not. Since no other Linux balloon driver (hv, Xen, virtio) uses sleeping allocations, use the same approach. We do distinguish, however, between 2MB allocations and 4kB allocations and prevent reclamation on 2MB. In both cases, we avoid using emergency low-memory pools, as it may cause undesired effects. Reviewed-by:
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Nadav Amit authored
The use of accessors for batch entries complicates the code and makes it less readable. Remove it an instead use bit-fields. Reviewed-by:
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Nadav Amit authored
The lock and unlock code paths are very similar, so avoid the duplicate code by merging them together. Reviewed-by:
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Nadav Amit authored
Now that we have a single point, unify the tracing and collecting the statistics for commands and their failure. While it might somewhat reduce the control over debugging, it cleans the code a lot. Reviewed-by:
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Nadav Amit authored
By inlining the hypercall interface, we can unify several operations into one central point in the code: - Updating the target. - Updating when a reset is needed. - Update statistics (which will be done later in the patch-set). - Print debug-messages (although they cannot be enabled as selectively). Reviewed-by:
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zhong jiang authored
of_node_put and put_device has taken the null pointer check into account. So it is safe to remove the duplicated check. Signed-off-by:
zhong jiang <zhongjiang@huawei.com> Signed-off-by:
Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
While we updated the coresight DT bindings, some of the new examples were not updated due to the order in which they were merged. Let us update all the missed out ones to the new bindings to avoid confusion. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Rob Herring <robh@kernel.org> Cc: Frank Rowand <frowand.list@gmail.com> Signed-off-by:
Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Suzuki K Poulose authored
TPIU component has an input port. The example uses out-ports which is wrong. Let us fix it. Reported-by:
Leo Yan <leo.yan@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
Use CLAIM protocol to make sure the device is available for use. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
Use the CLAIM protocol to grab the ownership of the component when in use. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
Use the CLAIM protocol to grab the ownership of the component. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
Use the CLAIM tags to grab the device for self-hosted usage. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
Coresight architecture defines CLAIM tags for a device to negotiate control of the components (external agent vs self-hosted). Each device has a pair of registers (CLAIMSET & CLAIMCLR) for managing the CLAIM tags. However, the protocol for the CLAIM tags is IMPLEMENTATION DEFINED. PSCI has recommendations for the use of the CLAIM tags to negotiate controls for external agent vs self-hosted use. This patch implements the recommended protocol by PSCI. The claim/disclaim operations are performed from the device specific drivers. The disadvantage is that the calls are sprinkled in each driver, but this makes the operation much simpler. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
When a replicator port is enabled, we block the traffic on the other port and route all traffic to the new enabled port. If there are two active trace sessions each targeting the two different paths from the replicator, the second session will disable the first session and route all the data to the second path. ETR / e.g, replicator \ ETB If CPU0 is operated in sysfs mode to ETR and CPU1 is operated in perf mode to ETB, depending on the order in which the replicator is enabled one device is blocked. Ideally we need trace-id for the session to make the right choice. That implies we need a trace-id allocation logic for the coresight subsystem and use that to route the traffic. The short term solution is to only manage the "target port" and leave the other port untouched. That leaves both the paths unaffected, except that some unwanted traffic may be pushed to the paths (if the Trace-IDs are not far enough), which is still fine and can be filtered out while processing rather than silently blocking the data. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: -
Suzuki K Poulose authored
Prepare the etb10 driver to return errors in enabling the device. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
Add support for reporting errors back from the SMP cross function call for enabling ETM. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
Add support for handling errors in enabling the component. The ETM is enabled via cross call to owner CPU. Make necessary changes to report the error back from the cross call. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
Prepare to handle errors in enabling the hardware and report it back to the core driver. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
Make sure we honor the errors in CATU device and abort the operation. While at it, delay setting the etr_buf for the session until we are sure that we are indeed enabling the ETR. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
Refactor the tmc-etr enable operation to make it easier to handle errors in enabling the hardware. We need to make sure that the buffer is compatible with the ETR. This patch re-arranges to make the error handling easier, by deferring the hardware enablement until all the errors are checked. This also avoids turning the CATU on/off during a sysfs read session. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
coresight_enable_path() enables the components in a trace path from a given source to a sink, excluding the source. The operation is performed in the reverse order; the sink first and then backwards in the list. However, if we encounter an error in enabling any of the component, we simply disable all the components in the given path irrespective of whether we enabled some of the components in the enable iteration. This could interfere with another trace session if one of the link devices is turned off (e.g, TMC-ETF). So, we need to make sure that we only disable those components which were actually enabled from the iteration. This patch achieves the same by refactoring the coresight_disable_path to accept a "node" to start from in the forward order, which can then be used from the error path of coresight_enable_path(). With this change, we don't issue a disable call back for a component which didn't get enabled. This change of behavior triggers a bug in coresight_enable_link(), where we leave the refcount on the device and will prevent the device from being enabled forever. So, we also drop the refcount in the coresight_enable_link() if the operation failed. Also, with the refactoring, we always start after the first node (which is the "SOURCE" device) for disabling the entire path. This implies, we must not find a "SOURCE" in the middle of the path. Hence, added a WARN_ON() to make sure the paths we get are sane, rather than simply ignoring them. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Leo Yan authored
>From the comment in the code, it claims the requirement for byte-address alignment for RRP register: 'for 32-bit, 64-bit and 128-bit wide trace memory, the four LSBs must be 0s. For 256-bit wide trace memory, the five LSBs must be 0s'. This isn't consistent with the program, the program sets five LSBs as zeros for 32/64/128-bit wide trace memory and set six LSBs zeros for 256-bit wide trace memory. After checking with the CoreSight Trace Memory Controller technical reference manual (ARM DDI 0461B, section 3.3.4 RAM Read Pointer Register), it proves the comment is right and the program does wrong setting. This patch fixes byte-address alignment for RRP by following correct definition in the technical reference manual. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by:
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Leo Yan authored
In ETB dump function tmc_etb_dump_hw() it has nested loops. The second level loop is to iterate index in the range [0 .. drvdata->memwidth); but the index isn't really used in the code, thus the second level loop is useless. This patch is to remove the second level loop; the refactor also reduces indentation and we can use 'break' to replace 'goto' tag. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Tomasz Nowicki authored
For non-VHE systems host kernel runs at EL1 and jumps to EL2 whenever hypervisor code should be executed. In this case ETM4x driver must restrict configuration to EL1 when it setups kernel tracing. However, there is no separate hypervisor privilege level when VHE is enabled, the host kernel runs at EL2. This patch fixes configuration of TRCACATRn register for VHE systems so that ETM_EXLEVEL_NS_HYP bit is used instead of ETM_EXLEVEL_NS_OS to on/off kernel tracing. At the same time, it moves common code to new helper. Signed-off-by:
Tomasz Nowicki <tnowicki@caviumnetworks.com> Signed-off-by:
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Mathieu Poirier authored
Up until now the relative simplicity of enabling the ETB made it possible to accommodate processing for both sysFS and perf methods. But work on claimtags and CPU-wide trace scenarios is adding some complexity, making the current code messy and hard to maintain. As such follow what has been done for ETF and ETR components and split function etb_enable() so that processing for both API can be done cleanly. Signed-off-by:
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Mathieu Poirier authored
This patch moves the etb_drvdata::mode from a locat_t to a simple u32, as it is for the ETF and ETR drivers. This streamlines the code and adds commonality with the other drivers when dealing with similar operations. Signed-off-by:
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Suzuki K Poulose authored
Add support for using TMC-ETR as backend for ETM perf tracing. We use software double buffering at the moment. i.e, the TMC-ETR uses a separate buffer than the perf ring buffer. The data is copied to the perf ring buffer once a session completes. The TMC-ETR would try to match the larger of perf ring buffer or the ETR buffer size configured via sysfs, scaling down to a minimum limit of 1MB. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
In coresight perf mode, we need to prepare the sink before starting a session, which is done via set_buffer call back. We then proceed to enable the tracing. If we fail to start the session successfully, we leave the sink configuration unchanged. In order to make the operation atomic and to avoid yet another call back to clear the buffer, we get rid of the "set_buffer" call back and pass the buffer details via enable() call back to the sink. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
We can always find the sink configuration for a given perf_output_handle. Add a helper to retrieve the sink configuration for a given perf_output_handle. This will be used to get rid of the set_buffer() call back. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
Right now we issue an update_buffer() and reset_buffer() call backs in succession when we stop tracing an event. The update_buffer is supposed to check the status of the buffer and make sure the ring buffer is updated with the trace data. And we store information about the size of the data collected only to be consumed by the reset_buffer callback which always follows the update_buffer. This was originally designed for handling future IPs which could trigger a buffer overflow interrupt. This patch gets rid of the reset_buffer callback altogether and performs the actions in update_buffer, making it return the size collected. We can always add the support for handling the overflow interrupt case later. This removes some not-so pretty hack (storing the new head in the size field for snapshot mode) and cleans it up a little bit. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
Convert component enable/disable messages from dev_info to dev_dbg. When used with perf, the components in the paths are enabled/disabled during each schedule of the run, which can flood the dmesg with these messages. Moreover, they are only useful for debug purposes. So, convert such messages to dev_dbg() which can be turned on as needed. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
Since the ETR now uses mode specific buffers, we can reliably provide the trace data captured in sysfs mode, even when the ETR is operating in PERF mode. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
Since the ETR could be driven either by SYSFS or by perf, it becomes complicated how we deal with the buffers used for each of these modes. The ETR driver cannot simply free the current attached buffer without knowing the provider (i.e, sysfs vs perf). To solve this issue, we provide: 1) the driver-mode specific etr buffer to be retained in the drvdata 2) the etr_buf for a session should be passed on when enabling the hardware, which will be stored in drvdata->etr_buf. This will be replaced (not free'd) as soon as the hardware is disabled, after necessary sync operation. The advantages of this are : 1) The common code path doesn't need to worry about how to dispose an existing buffer, if it is about to start a new session with a different buffer, possibly in a different mode. 2) The driver mode can control its buffers and can get access to the saved session even when the hardware is operating in a different mode. (e.g, we can still access a trace buffer from a sysfs mode even if the etr is now used in perf mode, without disrupting the current session.) Towards this, we introduce a sysfs specific data which will hold the etr_buf used for sysfs mode of operation, controlled solely by the sysfs mode handling code. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
We enable the trace path, before activating the source. If we fail to enable the source, we must disable the path to make sure it is available for another session. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
At the moment, if there is no CPU specified for a given event, we use cpu_online_mask and try to build path for each of the CPUs in the mask. This could prevent any CPU that is turned online later to be used for the tracing. This patch changes to use the cpu_present_mask and tries to build path for as much CPUs as possible ignoring the failures in building path for some of the CPUs. If ever we try to trace on those CPUs, we fail the operation. Based on a patch from Mathieu Poirier. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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