- 31 Aug, 2011 15 commits
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Mark Rutland authored
This patch moves the active_events counter into struct arm_pmu, in preparation for supporting multiple PMUs. This also moves pmu_reserve_mutex, as it is used to guard accesses to active_events. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Reviewed-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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Mark Rutland authored
Currently, pmu_hw_events::active_mask is used to keep track of which events are active in hardware. As we can stop counters and their interrupts, this is unnecessary. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Reviewed-by: Jamie Iles <jamie@jamieiles.com> Reviewed-by: Ashwin Chaugule <ashwinc@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
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Mark Rutland authored
Currently, event group validation compares each event's 'pmu' pointer against the static 'pmu' pointer. This limits the code to supporting only 1 PMU. This patch changes the behaviour to consider an event's group leader's 'pmu' pointer as canonical for validation. This should ease later generalisation of the code to support multiple PMUs at once. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Reviewed-by: Jamie Iles <jamie@jamieiles.com> Reviewed-by: Ashwin Chaugule <ashwinc@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
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Mark Rutland authored
Currently, an "empty" struct pmu is registered as the CPU PMU, regardless of whether there is a physical PMU. This burdens the accessor functions with checks to see whether a PMU is actually present. This patch changes initialisation to register a PMU only if there is a supported PMU present, and removes the checks that this change makes redundant. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Reviewed-by: Jamie Iles <jamie@jamieiles.com> Reviewed-by: Ashwin Chaugule <ashwinc@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
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Mark Rutland authored
Currently, an event's 'pmu' field is set after pmu::event_init() is called. This means that pmu::event_init() must figure out which struct pmu the event was initialised from. This makes it difficult to consolidate common event initialisation code for similar PMUs, and very difficult to implement drivers for PMUs which can have multiple instances (e.g. a USB controller PMU, a GPU PMU, etc). This patch sets the 'pmu' field before initialising the event, allowing event init code to identify the struct pmu instance easily. In the event of failure to initialise an event, the event is destroyed via kfree() without calling perf_event::destroy(), so this shouldn't result in bad behaviour even if the destroy field was set before failure to initialise was noted. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/1313062280-19123-1-git-send-email-mark.rutland@arm.comSigned-off-by: Ingo Molnar <mingo@elte.hu>
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Will Deacon authored
The Cortex-A15 PMU implements the PMUv2 specification and therefore has support for some mode exclusion. This patch adds support for excluding user, kernel and hypervisor counts from a given event. Acked-by: Jamie Iles <jamie@jamieiles.com> Reviewed-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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Will Deacon authored
Modern PMUs allow for mode exclusion, so we no longer wish to return -EPERM if it is requested. This patch provides a hook in the armpmu structure for implementing mode exclusion. The hw_perf_event initialisation is slightly delayed so that the backend code can update the structure if required. Acked-by: Jamie Iles <jamie@jamieiles.com> Reviewed-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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Will Deacon authored
ARM PMU code used to use 1-based indices for PMU registers. This caused several data structures (pmu_hw_events::{active_events, used_mask, events}) to have an unused element at index zero. ARMPMU_MAX_HWEVENTS still takes this indexing into account, and currently equates to 33. This patch updates the core ARM perf code to use the 0th index again. Acked-by: Jamie Iles <jamie@jamieiles.com> Reviewed-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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Will Deacon authored
Now that the ARMv7 PMU backend indexes event counters from zero, follow suit and do the same for ARMv6 and Xscale. Acked-by: Jamie Iles <jamie@jamieiles.com> Reviewed-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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Will Deacon authored
The current ARMv7 PMU backend indexes event counters from two, with index zero being reserved and index one being used to represent the cycle counter. This patch tidies up the code by indexing from one instead (with zero for the cycle counter). This allows us to remove many of the accessor macros along with the counter enumeration and makes the code much more readable. Acked-by: Jamie Iles <jamie@jamieiles.com> Reviewed-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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Will Deacon authored
This patch ensures that integers are used to represent event indices in the ARMv7 PMU backend. This ensures consistency between functions and also with the arm_pmu structure. Acked-by: Jamie Iles <jamie@jamieiles.com> Reviewed-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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Will Deacon authored
The ARMv7 perf backend mixes up u32 and unsigned long, which is rather ugly. This patch makes the ARMv7 PMU code consistently use the u32 type instead. Acked-by: Jamie Iles <jamie@jamieiles.com> Reviewed-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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Will Deacon authored
Commit 5dfc54e0 ("ARM: GIC: avoid routing interrupts to offline CPUs") prevents the GIC from setting the affinity of an IRQ to a CPU with id >= nr_cpu_ids. This was previously abused by perf on some platforms where more IRQs were registered than possible CPUs. This patch fixes the problem by using a cpumask_t to keep track of the active (requested) interrupts in perf. The same effect could be achieved by limiting the number of IRQs to the number of CPUs, but using a mask instead will be useful for adding extended CPU hotplug support in the future. Acked-by: Jamie Iles <jamie@jamieiles.com> Reviewed-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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Will Deacon authored
Once upon a time, OProfile and Perf fought hard over who could play with the PMU. To stop all hell from breaking loose, pmu.c offered an internal reserve/release API and took care of parsing PMU platform data passed in from board support code. Now that Perf has ingested OProfile, let's move the platform device handling into the Perf driver and out of the PMU locking code. Unfortunately, the lock has to remain to prevent Perf being bitten by out-of-tree modules such as LTTng, which still claim a right to the PMU when Perf isn't looking. Acked-by: Jamie Iles <jamie@jamieiles.com> Reviewed-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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Mark Rutland authored
This patch removes const qualifiers from instances of struct arm_pmu, and functions initialising them, in preparation for generalising arm_pmu usage to system (AKA uncore) PMUs. This will allow for dynamically modifiable structures (locks, struct pmu) to be added as members of struct arm_pmu. Acked-by: Jamie Iles <jamie@jamieiles.com> Reviewed-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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- 29 Aug, 2011 21 commits
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Linus Torvalds authored
* 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm: ARM: pm: avoid writing the auxillary control register for ARMv7 ARM: pm: some ARMv7 requires a dsb in resume to ensure correctness ARM: pm: arm920/926: fix number of registers saved ARM: pm: CPU specific code should not overwrite r1 (v:p offset) ARM: 7066/1: proc-v7: disable SCTLR.TE when disabling MMU ARM: 7065/1: kexec: ensure new kernel is entered in ARM state ARM: 7003/1: vexpress: Add clock definition for the SP805. ARM: 7051/1: cpuimx* boards: fix mach-types errors ARM: 7019/1: Footbridge: select CLKEVT_I8253 for ARCH_NETWINDER ARM: 7015/1: ARM errata: Possible cache data corruption with hit-under-miss enabled ARM: 7014/1: cache-l2x0: Fix L2 Cache size calculation. ARM: 6967/1: ep93xx: ts72xx: fix board model detection ARM: 6965/1: ep93xx: add model detection for ts-7300 and ts-7400 boards ARM: cache: detect VIPT aliasing I-cache on ARMv6 ARM: twd: register clockevents device before enabling PPI ARM: realview: ensure visibility of writes during reset ARM: perf: make name of arm_pmu_type consistent ARM: perf: fix prototype of release_pmu ARM: fix perf build with uclibc toolchains
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-socLinus Torvalds authored
* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: ARM: mach-footbridge: add missing header file <video/vga.h> ARM: mach-orion5x: add missing header file <linux/vga.h> arm: fix compile failure in orion5x/dns323-setup.c at91: at91sam9261.c: fix typo in t2_clk alias for atmel_tcb.0 ARM: S5P: fix bug in spdif_clk_get_rate ARM: EXYNOS4: Add restart hook for proper reboot ARM: EXYNOS4: Increase reset delay for USB HOST PHY ARM: S5P: add required chained_irq_enter/exit to gpio-int code ARM: EXYNOS4: add required chained_irq_enter/exit to eint code ARM: SAMSUNG: Add chained enrty/exit call to timer interrupt handler ARM: S3C64XX: Fix build break in PM debug ARM: S5PV210: Fix build warning ARM: EXYNOS4: Fix the IRQ definitions for MIPI CSIS device ARM: EXYNOS4: remove duplicated inclusion ARM: EXYNOS4: Fix wrong devname to support clkdev ARM: EXYNOS4: Use the correct regulator names on universal_c210 ARM: SAMSUNG: Fix Section mismatch in samsung_bl_set() ARM: S5P64X0: Replace irq_gc_ack() with irq_gc_ack_set_bit()
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Stephen Rothwell authored
These were missed in commit f5b94099 "All Arch: remove linkage for sys_nfsservctl system call" due to them having no sys_ prefix (presumably). Cc: NeilBrown <neilb@suse.de> Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-parisc@vger.kernel.org Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Acked-by: James Bottomley <James.Bottomley@hansenpartnership.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/davem/netLinus Torvalds authored
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (42 commits) netpoll: fix incorrect access to skb data in __netpoll_rx cassini: init before use in cas_interruptN. can: ti_hecc: Fix uninitialized spinlock in probe can: ti_hecc: Fix unintialized variable net: sh_eth: fix the compile error net/phy: fix DP83865 phy interrupt handler sendmmsg/sendmsg: fix unsafe user pointer access ibmveth: Fix leak when recycling skb and hypervisor returns error arp: fix rcu lockdep splat in arp_process() bridge: fix a possible use after free bridge: Pseudo-header required for the checksum of ICMPv6 mcast: Fix source address selection for multicast listener report MAINTAINERS: Update GIT trees for network development ath9k: Fix PS wrappers in ath9k_set_coverage_class carl9170: Fix mismatch in carl9170_op_set_key mutex lock-unlock wl12xx: add max_sched_scan_ssids value to the hw description wl12xx: Fix validation of pm_runtime_get_sync return value wl12xx: Remove obsolete testmode NVS push command bcma: add uevent to the bus, to autoload drivers ath9k_hw: Fix STA (AR9485) bringup issue due to incorrect MAC address ...
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git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparcLinus Torvalds authored
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc: sparc32,sun4d: Change IPI IRQ level to prevent collision between IPI and timer interrupt sparc: Remove another reference to nfsservctl
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Linus Torvalds authored
Merge branch 'rmobile-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-3.x * 'rmobile-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-3.x: ARM: mach-shmobile: sh7372 CMT3 and CMT4 clock support ARM: mach-shmobile: sh7372 MSIOF clock support ARM: mach-shmobile: clock-sh7372: fixup USB-DMAC1 settings ARM: mach-shmobile: clock-sh73a0: tidyup CKSCR main clock selecter ARM: mach-shmobile: Remove 3DG/SGX from sh7372 INTCS ARM: mach-shmobile: mackerel: Add USB-DMA ID mmc: sdhi, mmcif: zboot: Correct clock disable logic ARM: mach-shmobile: ag5evm: SDHI requires waiting for idle ARM: static should be at beginning of declaration ARM: mach-shmobile: Use CMT2 for timer on sh7372 ARM: mach-shmobile: sh7372: Add USB-DMAC support
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git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-3.xLinus Torvalds authored
* 'sh-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-3.x: sh: fix the compile error in setup-sh7757.c serial: sh-sci: report CTS as active for get_mctrl sh: Add unaligned memory access for PC relative intructions sh: Fix unaligned memory access for branches without delay slots sh: Fix up fallout from cpuidle changes. serial: sh-sci: console Runtime PM support sh: Fix conflicting definitions of ptrace_triggered serial: sh-sci: fix DMA build by including dma-mapping.h serial: sh-sci: Fix up default regtype probing. sh: intc: enable both edges GPIO interrupts on sh7372 shwdt: fix usage of mod_timer clocksource: sh_cmt: wait for CMCNT on init V2
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Florian Tobias Schandinat authored
As Paul has not much time for it I take over maintaining the framebuffer subsystem. Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de> Acked-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Kjetil Oftedal authored
On Sun4d systems running in SMP mode, IRQ 14 is used for timer interrupts and has a specialized interrupt handler. IPI is currently set to use IRQ 14 as well, which causes it to trigger the timer interrupt handler, and not the IPI interrupt handler. The IPI interrupt is therefore changed to IRQ 13, which is the highest normally handled interrupt. This IRQ is also used for SBUS interrupts, however there is nothing in the IPI/SBUS interrupt handlers that indicate that they will not handle sharing the interrupt. (IRQ 13 is indicated as audio interrupt, which is unlikely to be found in a sun4d system) Signed-off-by: Kjetil Oftedal <oftedal@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Stephen Rothwell authored
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: David S. Miller <davem@davemloft.net>
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Magnus Damm authored
Add clock control support for sh7372 CMT hardware blocks. No upstream sh7372 boards are making use of CMT3 + CMT4, but the sh7372 hardware happens to come out of reset with all CMT MSTP clocks _enabled_, so to save power we need to implement a fix in software to shut down unused clocks. This patch relies on the recently merged 794d78fe drivers: sh: late disabling of clocks V2 to make sure the unused clocks get disabled as expected. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Magnus Damm authored
Add clock control support for sh7372 MSIOF hardware blocks. No upstream sh7372 boards are making use of MSIOF0->2, but the sh7372 hardware happens to come out of reset with all MSIOF MSTP clocks _enabled_, so to save power we need to implement a fix in software to shut down unused clocks. This patch relies on the recently merged 794d78fe drivers: sh: late disabling of clocks V2 to make sure the unused clocks get disabled as expected. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Kuninori Morimoto authored
USB-DMAC1 needs SMSTPCR4/MSTP407 controls, not MSTP214 this patch tested on mackerel board Reported-by: Magnus Damm <damm@opensource.se> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Kuninori Morimoto authored
MAINCKSEL is [29:28], not [27:24] Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Magnus Damm authored
This patch removes support for the SGX interrupt source in the sh7372 INTCS controller. The SGX hardware block included in sh7372 is already hooked up to the ARM Cortex-A8 core using the INTCA controller, so SGX users are encouraged to make use of that interrupt source instead. Removing support for the SGX interrupt source in INTCS simplifies the sh7372 power management code by allowing us to assume that only INTCA needs to be powered on to operate the SGX hardware. If the INTCS interrupt source would be kept then the kernel would be forced to deal with additional dependencies that does not follow the regular power domain hiearachy. With this patch in place we can safely power down INTCS while the SGX is operating. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
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Yoshihiro Shimoda authored
Fix the following build errors: CC arch/sh/kernel/cpu/sh4a/setup-sh7757.o arch/sh/kernel/cpu/sh4a/setup-sh7757.c:681: error: implicit declaration of function ‘DMA_BIT_MASK’ arch/sh/kernel/cpu/sh4a/setup-sh7757.c:681: error: initializer element is not constant arch/sh/kernel/cpu/sh4a/setup-sh7757.c:681: error: (near initialization for ‘usb_ehci_device.dev.coherent_dma_mask’) arch/sh/kernel/cpu/sh4a/setup-sh7757.c:705: error: initializer element is not constant arch/sh/kernel/cpu/sh4a/setup-sh7757.c:705: error: (near initialization for ‘usb_ohci_device.dev.coherent_dma_mask’) make[3]: *** [arch/sh/kernel/cpu/sh4a/setup-sh7757.o] Error 1 Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Yoshii Takashi authored
sh-sci.c sets hardware up and then let the HW do all flow controls. There is no software code, nor needs to get/set real CTS signal. But, when turning CRTSCTS on through termios, uart_set_termios() in serial_core.c checks CTS, and stops TX if it is inactive at the moment. Because sci_get_mctrl() returns a fixed value DTR|RTS|DSR but CTS, the sequence open -> set CRTSCTS -> write hit the case and stop working, no more outputs. This patch makes sci_get_mctrl() report CTS in addition. Signed-off-by: Takashi YOSHII <takashi.yoshii.zj@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Phil Edworthy authored
This adds unaligned memory access support for the following instructions: mov.w @(disp,PC),Rn mov.l @(disp,PC),Rn These instructions are often used on SH2A toolchains. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Phil Edworthy authored
This patch just clears the return code for those cases where an unaligned memory access occurs on branch instructions without a delay slot. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Linus Torvalds authored
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- 28 Aug, 2011 4 commits
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git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pmLinus Torvalds authored
* 'pm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: ARM: mach-shmobile: sh7372 LCDC1 suspend fix V2 (incremental) OMAP: omap_device: only override _noirq methods, not normal suspend/resume PM / Runtime: Correct documentation of pm_runtime_irq_safe() ARM: mach-shmobile: sh7372 LCDC1 suspend fix sh-sci / PM: Use power.irq_safe PM: Use spinlock instead of mutex in clock management functions
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Russell King authored
For ARMv7 kernels running in the non-secure world, writing to the auxillary control register causes an abort, so we must avoid directly writing the auxillary control register. If the ACR has already been reinitialized by SoC code, don't try to restore it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Add a dsb after the isb to ensure that the previous writes to the CP15 registers take effect before we enable the MMU. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
ARM920 and ARM926 save four registers, not three. Fix the size of the suspend region required. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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