- 03 Aug, 2017 3 commits
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Gustavo A. R. Silva authored
Remove unnecessary static on local variable dd. Such variable is initialized before being used, on every execution path throughout the function. The static has no benefit and, removing it reduces the object file size. This issue was detected using Coccinelle and the following semantic patch: https://github.com/GustavoARSilva/coccinelle/blob/master/static/static_unused.cocci In the following log you can see a difference in the object file size. This log is the output of the size command, before and after the code change: before: text data bss dec hex filename 26135 11944 128 38207 953f drivers/crypto/omap-sham.o after: text data bss dec hex filename 26084 11856 64 38004 9474 drivers/crypto/omap-sham.o Signed-off-by:
Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
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Rob Herring authored
Now that we have a custom printf format specifier, convert users of full_name to use %pOF instead. This is preparation to remove storing of the full path string for each node. Signed-off-by:
Rob Herring <robh@kernel.org> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: "David S. Miller" <davem@davemloft.net> Cc: linux-crypto@vger.kernel.org Signed-off-by:
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Horia Geantă authored
Add support for using the caam/jr backend on DPAA2-based SoCs. These have some particularities we have to account for: -HW S/G format is different -Management Complex (MC) firmware initializes / manages (partially) the CAAM block: MCFGR, QI enablement in QICTL, RNG Signed-off-by:
Horia Geantă <horia.geanta@nxp.com> Signed-off-by:
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- 28 Jul, 2017 14 commits
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Gary R Hook authored
A version 5 CCP can handle an RSA modulus up to 16k bits. Signed-off-by:
Gary R Hook <gary.hook@amd.com> Signed-off-by:
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Gary R Hook authored
Wire up the CCP as an RSA cipher provider. Signed-off-by:
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Gary R Hook authored
Signed-off-by:
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Gary R Hook authored
Version 5 devices have requirements for buffer lengths, as well as parameter format (e.g. bits vs. bytes). Fix the base CCP driver code to meet requirements all supported versions. Signed-off-by:
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Gary R Hook authored
Some updates this year have not had copyright dates changed in modified files. Correct this for 2017. Signed-off-by:
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Jason A. Donenfeld authored
Otherwise, we might be seeding the RNG using bad randomness, which is dangerous. The one use of this function from within the kernel -- not from userspace -- is being removed (keys/big_key), so that call site isn't relevant in assessing this. Cc: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by:
Jason A. Donenfeld <Jason@zx2c4.com> Signed-off-by:
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lionel.debieve@st.com authored
This module register a HASH module that support multiples algorithms: MD5, SHA1, SHA224, SHA256. It includes the support of HMAC hardware processing corresponding to the supported algorithms. DMA or IRQ mode are used depending on data length. Signed-off-by:
Lionel Debieve <lionel.debieve@st.com> Signed-off-by:
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lionel.debieve@st.com authored
This adds documentation of device tree bindings for the STM32 HASH controller. Signed-off-by:
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lionel.debieve@st.com authored
The complete stm32 module is rename as crypto in order to use generic naming Signed-off-by:
Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by:
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lionel.debieve@st.com authored
Use the correct unregister_shashes function to to remove the registered algo Signed-off-by:
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lionel.debieve@st.com authored
In case of arm soc support, readl and writel will be optimized using relaxed functions Signed-off-by:
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Xulin Sun authored
kill_fq removes a complete frame queue, it needs to free the qman_fq in the last. Else kmemleak will report the below warning: unreferenced object 0xffff800073085c80 (size 128): comm "cryptomgr_test", pid 199, jiffies 4294937850 (age 67.840s) hex dump (first 32 bytes): 00 00 00 00 00 00 00 00 a0 80 7e 00 00 80 ff ff 00 00 00 00 00 00 00 00 04 00 04 00 5c 01 00 00 backtrace: [<ffff8000001e5760>] create_object+0xf8/0x258 [<ffff800000994e38>] kmemleak_alloc+0x58/0xa0 [<ffff8000001d5f18>] kmem_cache_alloc_trace+0x2c8/0x358 [<ffff8000007e8410>] create_caam_req_fq+0x40/0x170 [<ffff8000007e870c>] caam_drv_ctx_update+0x54/0x248 [<ffff8000007fca54>] aead_setkey+0x154/0x300 [<ffff800000452120>] setkey+0x50/0xf0 [<ffff80000045b144>] __test_aead+0x5ec/0x1028 [<ffff80000045c28c>] test_aead+0x44/0xc8 [<ffff80000045c368>] alg_test_aead+0x58/0xd0 [<ffff80000045bdb4>] alg_test+0x14c/0x308 [<ffff8000004588e8>] cryptomgr_test+0x50/0x58 [<ffff8000000c3b2c>] kthread+0xdc/0xf0 [<ffff800000083c00>] ret_from_fork+0x10/0x50 And check where the function kill_fq() is called to remove the additional kfree to qman_fq and avoid re-calling the released qman_fq. Signed-off-by:Xulin Sun <xulin.sun@windriver.com> Acked-by:
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Stephan Mueller authored
The updated memory management is described in the top part of the code. As one benefit of the changed memory management, the AIO and synchronous operation is now implemented in one common function. The AF_ALG operation uses the async kernel crypto API interface for each cipher operation. Thus, the only difference between the AIO and sync operation types visible from user space is: 1. the callback function to be invoked when the asynchronous operation is completed 2. whether to wait for the completion of the kernel crypto API operation or not The change includes the overhaul of the TX and RX SGL handling. The TX SGL holding the data sent from user space to the kernel is now dynamic similar to algif_skcipher. This dynamic nature allows a continuous operation of a thread sending data and a second thread receiving the data. These threads do not need to synchronize as the kernel processes as much data from the TX SGL to fill the RX SGL. The caller reading the data from the kernel defines the amount of data to be processed. Considering that the interface covers AEAD authenticating ciphers, the reader must provide the buffer in the correct size. Thus the reader defines the encryption size. Signed-off-by:
Stephan Mueller <smueller@chronox.de> Signed-off-by:
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Stephan Mueller authored
The updated memory management is described in the top part of the code. As one benefit of the changed memory management, the AIO and synchronous operation is now implemented in one common function. The AF_ALG operation uses the async kernel crypto API interface for each cipher operation. Thus, the only difference between the AIO and sync operation types visible from user space is: 1. the callback function to be invoked when the asynchronous operation is completed 2. whether to wait for the completion of the kernel crypto API operation or not In addition, the code structure is adjusted to match the structure of algif_aead for easier code assessment. The user space interface changed slightly as follows: the old AIO operation returned zero upon success and < 0 in case of an error to user space. As all other AF_ALG interfaces (including the sync skcipher interface) returned the number of processed bytes upon success and < 0 in case of an error, the new skcipher interface (regardless of AIO or sync) returns the number of processed bytes in case of success. Signed-off-by:
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- 18 Jul, 2017 23 commits
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Harald Freudenberger authored
When a user chooses a rng source via sysfs attribute this rng should be sticky, even when other sources with better quality to register. This patch introduces a simple way to remember the user's choice. This is reflected by a new sysfs attribute file 'rng_selected' which shows if the current rng has been chosen by userspace. The new attribute file shows '1' for user selected rng and '0' otherwise. Signed-off-by:
Harald Freudenberger <freude@linux.vnet.ibm.com> Reviewed-by:
PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> Signed-off-by:
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Harald Freudenberger authored
This patch rewoks the hwrng to always use the rng source with best entropy quality. On registation and unregistration the hwrng now tries to choose the best (= highest quality value) rng source. The handling of the internal list of registered rng sources is now always sorted by quality and the top most rng chosen. Signed-off-by:
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Tudor Ambarus authored
SELF condition has no meaning for the SERIAL sharing since the jobs are executed in the same DECO. Signed-off-by:
Tudor Ambarus <tudor-dan.ambarus@nxp.com> Signed-off-by:
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Horia Geantă authored
Clean up the code, as indicated by Coccinelle. Cc: Julia Lawall <julia.lawall@lip6.fr> Signed-off-by:
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Tudor Ambarus authored
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Horia Geantă authored
sg_to_sec4_sg_len() is no longer used since commit 479bcc7c ("crypto: caam - Convert authenc to new AEAD interface") Its functionality has been superseded by the usage of sg_nents_for_len() returning the number of S/G entries corresponding to the provided length. Signed-off-by:
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Horia Geantă authored
Change log level for some prints from dev_info() to dev_dbg(), low-level details are needed only when debugging. Signed-off-by:
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Horia Geantă authored
sg_sw_sec4.h header is not used by caam/qi, thus remove its inclusion. Signed-off-by:
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Horia Geantă authored
Since ARM64 commit 1dccb598 ("arm64: simplify dma_get_ops"), dma_ops no longer default to swiotlb_dma_ops, but to dummy_dma_ops. dma_ops have to be explicitly set in the driver - at least for ARM64. Fixes: 67c2315d ("crypto: caam - add Queue Interface (QI) backend support") Signed-off-by:
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Horia Geantă authored
Associated data (AD) length is read by CAAM from an S/G entry that is initially filled by the GPP. Accordingly, AD length has to be stored in CAAM endianness. Fixes: b189817c ("crypto: caam/qi - add ablkcipher and authenc algorithms") Signed-off-by:
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Horia Geantă authored
For more than 16 S/G entries, driver currently corrupts memory on ARMv8, see below KASAN log. Note: this does not reproduce on PowerPC due to different (smaller) cache line size - 64 bytes on PPC vs. 128 bytes on ARMv8. One such use case is one of the cbc(aes) test vectors - with 8 S/G entries and src != dst. Driver needs 1 (IV) + 2 x 8 = 17 entries, which goes over the 16 S/G entries limit: (CAAM_QI_MEMCACHE_SIZE - offsetof(struct ablkcipher_edesc, sgt)) / sizeof(struct qm_sg_entry) = 256 / 16 = 16 S/Gs Fix this by: -increasing object size in caamqicache pool from 512 to 768; this means the maximum number of S/G entries grows from (at least) 16 to 32 (again, for ARMv8 case of 128-byte cache line) -add checks in the driver to fail gracefully (ENOMEM) in case the 32 S/G entries limit is exceeded ================================================================== BUG: KASAN: slab-out-of-bounds in ablkcipher_edesc_alloc+0x4ec/0xf60 Write of size 1 at addr ffff800021cb6003 by task cryptomgr_test/1394 CPU: 3 PID: 1394 Comm: cryptomgr_test Not tainted 4.12.0-rc7-next-20170703-00023-g72badbcc1ea7-dirty #26 Hardware name: LS1046A RDB Board (DT) Call trace: [<ffff20000808ac6c>] dump_backtrace+0x0/0x290 [<ffff20000808b014>] show_stack+0x14/0x1c [<ffff200008d62c00>] dump_stack+0xa4/0xc8 [<ffff200008264e40>] print_address_description+0x110/0x26c [<ffff200008265224>] kasan_report+0x1d0/0x2fc [<ffff2000082637b8>] __asan_store1+0x4c/0x54 [<ffff200008b4884c>] ablkcipher_edesc_alloc+0x4ec/0xf60 [<ffff200008b49304>] ablkcipher_encrypt+0x44/0xcc [<ffff20000848a61c>] skcipher_encrypt_ablkcipher+0x120/0x138 [<ffff200008495014>] __test_skcipher+0xaec/0xe30 [<ffff200008497088>] test_skcipher+0x6c/0xd8 [<ffff200008497154>] alg_test_skcipher+0x60/0xe4 [<ffff2000084974c4>] alg_test.part.13+0x130/0x304 [<ffff2000084976d4>] alg_test+0x3c/0x68 [<ffff2000084938ac>] cryptomgr_test+0x54/0x5c [<ffff20000810276c>] kthread+0x188/0x1c8 [<ffff2000080836c0>] ret_from_fork+0x10/0x50 Allocated by task 1394: save_stack_trace_tsk+0x0/0x1ac save_stack_trace+0x18/0x20 kasan_kmalloc.part.5+0x48/0x110 kasan_kmalloc+0x84/0xa0 kasan_slab_alloc+0x14/0x1c kmem_cache_alloc+0x124/0x1e8 qi_cache_alloc+0x28/0x58 ablkcipher_edesc_alloc+0x244/0xf60 ablkcipher_encrypt+0x44/0xcc skcipher_encrypt_ablkcipher+0x120/0x138 __test_skcipher+0xaec/0xe30 test_skcipher+0x6c/0xd8 alg_test_skcipher+0x60/0xe4 alg_test.part.13+0x130/0x304 alg_test+0x3c/0x68 cryptomgr_test+0x54/0x5c kthread+0x188/0x1c8 ret_from_fork+0x10/0x50 Freed by task 0: (stack is not available) The buggy address belongs to the object at ffff800021cb5e00 which belongs to the cache caamqicache of size 512 The buggy address is located 3 bytes to the right of 512-byte region [ffff800021cb5e00, ffff800021cb6000) The buggy address belongs to the page: page:ffff7e0000872d00 count:1 mapcount:0 mapping: (null) index:0x0 compound_mapcount: 0 flags: 0xfffc00000008100(slab|head) raw: 0fffc00000008100 0000000000000000 0000000000000000 0000000180190019 raw: dead000000000100 dead000000000200 ffff800931268200 0000000000000000 page dumped because: kasan: bad access detected Memory state around the buggy address: ffff800021cb5f00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ffff800021cb5f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >ffff800021cb6000: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc ^ ffff800021cb6080: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc ffff800021cb6100: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc ================================================================== Fixes: b189817c ("crypto: caam/qi - add ablkcipher and authenc algorithms") Signed-off-by: -
Horia Geantă authored
caam/qi needs a fix similar to what was done for caam/jr in commit "crypto: caam/qi - properly set IV after {en,de}crypt", to allow for ablkcipher/skcipher chunking/streaming. Cc: <stable@vger.kernel.org> Fixes: b189817c ("crypto: caam/qi - add ablkcipher and authenc algorithms") Suggested-by:David Gstir <david@sigma-star.at> Signed-off-by:
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Horia Geantă authored
caam/qi driver fails to compile when CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y. Fix it by making the offending local per_cpu variable global. Cc: <stable@vger.kernel.org> Fixes: 67c2315d ("crypto: caam - add Queue Interface (QI) backend support") Reported-by:
kbuild test robot <fengguang.wu@intel.com> Signed-off-by:
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Horia Geantă authored
caam/qi driver does not compile when DEBUG is enabled (CRYPTO_DEV_FSL_CAAM_DEBUG=y): drivers/crypto/caam/caamalg_qi.c: In function 'ablkcipher_done': drivers/crypto/caam/caamalg_qi.c:794:2: error: implicit declaration of function 'dbg_dump_sg' [-Werror=implicit-function-declaration] dbg_dump_sg(KERN_ERR, "dst @" __stringify(__LINE__)": ", Since dbg_dump_sg() is shared between caam/jr and caam/qi, move it in a shared location and export it. At the same time: -reduce ifdeferry by providing a no-op implementation for !DEBUG case -rename it to caam_dump_sg() to be consistent in terms of exported symbols namespace (caam_*) Cc: <stable@vger.kernel.org> Fixes: b189817c ("crypto: caam/qi - add ablkcipher and authenc algorithms") Signed-off-by:
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Horia Geantă authored
s/desi/des for echainiv(authenc(hmac(sha256),cbc(des))) alg. Cc: <stable@vger.kernel.org> Fixes: b189817c ("crypto: caam/qi - add ablkcipher and authenc algorithms") Signed-off-by:
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Gustavo A. R. Silva authored
Check return value from call to of_match_device() in order to prevent a NULL pointer dereference. In case of NULL print error message and return -ENODEV Signed-off-by:
Gustavo A. R. Silva <garsilva@embeddedor.com> Signed-off-by:
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Chris Gorman authored
fixed WARNING: Block comments should align the * on each line fixed WARNINGs: Missing a blank line after declarations fixed ERROR: space prohibited before that ',' (ctx:WxE) Signed-off-by:
Chris Gorman <chrisjohgorman@gmail.com> Signed-off-by:
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Brijesh Singh authored
Since SP device driver supports multiples devices (e.g CCP, PSP), we should not fail the driver init just because CCP device is not found. Signed-off-by:
Brijesh Singh <brijesh.singh@amd.com> Acked-by:
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Brijesh Singh authored
CCP device initializes is now integerated into higher level SP device, to avoid the confusion lets rename the ccp driver initialization files (ccp-platform.c->sp-platform.c, ccp-pci.c->sp-pci.c). The patch does not make any functional changes other than renaming file and structures Signed-off-by:
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Brijesh Singh authored
The CCP and PSP devices part of AMD Secure Procesor may share the same interrupt. Hence we expand the SP device to register a common interrupt handler and provide functions to CCP and PSP devices to register their interrupt callback which will be invoked upon interrupt. Signed-off-by:
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Brijesh Singh authored
The CCP device is part of the AMD Secure Processor. In order to expand the usage of the AMD Secure Processor, create a framework that allows functional components of the AMD Secure Processor to be initialized and handled appropriately. Signed-off-by:
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Brijesh Singh authored
Update pci and platform files to use devres interface to allocate the PCI and iomap resources. Also add helper functions to consolicate module init, exit and power mangagement code duplication. Signed-off-by:
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Tudor-Dan Ambarus authored
A new cryptographic engine driver was added in drivers/crypto/atmel-ecc.*. Add myself as a maintainer for this driver. Signed-off-by:
Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by:
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