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- 08 Oct, 2018 12 commits
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Jisheng Zhang authored
If hosts provides ops->adma_write_desc, we should not fall back to the general sdhci_adma_write_desc(). Signed-off-by:
Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Chunyan Zhang authored
When Host Version 4 Enable is set to 1, SDMA uses ADMA System Address register (05Fh-058h) instead of using register (000h-004h) to indicate its system address of data location. The register (000h-004h) is re-assigned to 32-bit Block Count and Auto CMD23 argument, so then SDMA may use Auto CMD23. Signed-off-by:
Chunyan Zhang <zhang.chunyan@linaro.org> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Chunyan Zhang authored
As SD Host Controller Specification v4.10 documents: Host Controller Version 4.10 defines this "Auto CMD Auto Select" mode. Selection of Auto CMD depends on setting of CMD23 Enable in the Host Control 2 register which indicates whether card supports CMD23. If CMD23 Enable =1, Auto CMD23 is used and if CMD23 Enable =0, Auto CMD12 is used. In case of Version 4.10 or later, use of Auto CMD Auto Select is recommended rather than use of Auto CMD12 Enable or Auto CMD23 Enable. This patch add this new mode support. Signed-off-by:
Chunyan Zhang <zhang.chunyan@linaro.org> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Chunyan Zhang authored
Host Controller Version 4.10 re-defines SDMA System Address register as 32-bit Block Count for v4 mode, and SDMA uses ADMA System Address register (05Fh-058h) instead if v4 mode is enabled. Also when using 32-bit block count, 16-bit block count register need to be set to zero. Since using 32-bit Block Count would cause problems for auto-cmd23, it can be chosen via host->quirk2. Signed-off-by:
Chunyan Zhang <zhang.chunyan@linaro.org> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Chunyan Zhang authored
ADMA2 64-bit addressing support is divided into V3 mode and V4 mode. So there are two kinds of descriptors for ADMA2 64-bit addressing i.e. 96-bit Descriptor for V3 mode, and 128-bit Descriptor for V4 mode. 128-bit Descriptor is aligned to 8-byte. For V4 mode, ADMA2 64-bit addressing is enabled via Host Control 2 register. Signed-off-by:
Chunyan Zhang <zhang.chunyan@linaro.org> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> [Ulf: Fixed conflict while applying] Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Chunyan Zhang authored
According to the SD host controller specification version 4.10, when Host Version 4 is enabled, SDMA uses ADMA System Address register (05Fh-058h) instead of using SDMA System Address register to support both 32-bit and 64-bit addressing. Signed-off-by:
Chunyan Zhang <zhang.chunyan@linaro.org> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Chunyan Zhang authored
For SD host controller version 4.00 or later ones, there're two modes of implementation - Version 3.00 compatible mode or Version 4 mode. This patch introduced an interface to enable v4 mode. Signed-off-by:
Chunyan Zhang <zhang.chunyan@linaro.org> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Chunyan Zhang authored
Added definitions for v400, v410, v420. Signed-off-by:
Chunyan Zhang <zhang.chunyan@linaro.org> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Jisheng Zhang authored
Add this hook so that it can be overridden with driver specific implementations. We also let the original sdhci_adma_write_desc() accept &desc so that the function can set its new value. Then export the function so that it could be reused by driver's specific implementations. Signed-off-by:
Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Jisheng Zhang authored
This patch adds adma_table_cnt member to struct sdhci_host to give more flexibility to drivers to control the ADMA table count. Default value of adma_table_cnt is set to (SDHCI_MAX_SEGS * 2 + 1). Signed-off-by:
Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Aapo Vienamo authored
Allow SDHCI drivers to hook code before and after sdhci_request() by making it externally visible. Signed-off-by:
Aapo Vienamo <avienamo@nvidia.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Yinbo Zhu authored
This patch is to add tuning error codes to judge tuning state Signed-off-by:
Yinbo Zhu <yinbo.zhu@nxp.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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- 30 Jul, 2018 2 commits
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ernest.zhang authored
Add hardware tuning function instead of software tuning because O2/Bayhub SD host controller support hardware tuning. Signed-off-by:
ernest.zhang <ernest.zhang@bayhubtech.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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ernest.zhang authored
Export sdhci tuning function symbols which are used by other SD Host controller driver modules. Signed-off-by:
ernest.zhang <ernest.zhang@bayhubtech.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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- 16 Jul, 2018 1 commit
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Stefan Agner authored
For eMMC devices it is valid to only support 1.8V signaling. When vqmmc is set to a fixed 1.8V regulator the stack tries to set 3.3V initially and prints the following warning: mmc1: Switching to 3.3V signalling voltage failed Clear the MMC_SIGNAL_VOLTAGE_330 flag in case 3.3V is signaling is not available. This prevents the stack from even trying to use 3.3V signaling and avoids the above warning. Signed-off-by:
Stefan Agner <stefan@agner.ch> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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- 03 May, 2018 4 commits
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Kishon Vijay Abraham I authored
sdhci has a 10 second timeout to catch devices that stop responding. In the case of quirk SDHCI_QUIRK2_DISABLE_HW_TIMEOUT, instead of programming 10 second arbitrary value, calculate the total time it would take for the entire transfer to happen and program the timeout value accordingly. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Adrian Hunter authored
Factor out the target_timeout calculation so it can be re-used. Signed-off-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Adrian Hunter authored
Add quirk to disable HW timeout if the requested timeout is more than the maximum obtainable timeout. Also, if the quirk is set and ->get_max_timeout_count() is not implemented, max_busy_timeout is set to zero. Based-on-patch-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Kishon Vijay Abraham I authored
The SDHCI controller in a SoC might support HS200/HS400 (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property), but if the board is modeled such that the IO lines are not connected to 1.8v then HS200/HS400 cannot be supported. Disable HS200/HS400 if the board does not have 1.8v connected to the IO lines. Also Disable DDR/UHS in 1.8v if the IO lines are not connected to 1.8v. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Acked-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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- 05 Mar, 2018 2 commits
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Adrian Hunter authored
Do not enable wakeup for SDIO card interrupt unless the SDIO function driver has requested it which is indicated by mmc_card_wake_sdio_irq(). Signed-off-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Adrian Hunter authored
Do not unnecessarily enable card detect wakeup in the cases that the card is not removable or a GPIO is used for card detect. Signed-off-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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- 31 Jan, 2018 1 commit
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Linus Walleij authored
The bounce buffer is gone from the MMC core, and now we found out that there are some (crippled) i.MX boards out there that have broken ADMA (cannot do scatter-gather), and also broken PIO so they must use SDMA. Closer examination shows a less significant slowdown also on SDMA-only capable Laptop hosts. SDMA sets down the number of segments to one, so that each segment gets turned into a singular request that ping-pongs to the block layer before the next request/segment is issued. Apparently it happens a lot that the block layer send requests that include a lot of physically discontiguous segments. My guess is that this phenomenon is coming from the file system. These devices that cannot handle scatterlists in hardware can see major benefits from a DMA-contiguous bounce buffer. This patch accumulates those fragmented scatterlists in a physically contiguous bounce buffer so that we can issue bigger DMA data chunks to/from the card. When tested with a PCI-integrated host (1217:8221) that only supports SDMA: 0b:00.0 SD Host controller: O2 Micro, Inc. OZ600FJ0/OZ900FJ0/OZ600FJS SD/MMC Card Reader Controller (rev 05) This patch gave ~1Mbyte/s improved throughput on large reads and writes when testing using iozone than without the patch. dmesg: sdhci-pci 0000:0b:00.0: SDHCI controller found [1217:8221] (rev 5) mmc0 bounce up to 128 segments into one, max segment size 65536 bytes mmc0: SDHCI controller on PCI [0000:0b:00.0] using DMA On the i.MX SDHCI controllers on the crippled i.MX 25 and i.MX 35 the patch restores the performance to what it was before we removed the bounce buffers. Cc: Pierre Ossman <pierre@ossman.eu> Cc: Benoît Thébaudeau <benoit@wsystem.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Benjamin Beckmeyer <beckmeyer.b@rittal.de> Cc: stable@vger.kernel.org # v4.14+ Fixes: de3ee99b ("mmc: Delete bounce buffer handling") Tested-by:
Benjamin Beckmeyer <beckmeyer.b@rittal.de> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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- 17 Jan, 2018 3 commits
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Adrian Hunter authored
In preparation for adding more conditions for whether IRQ wakeup is enabled, rework sdhci_enable_irq_wakeups() so that needed bits are added instead of adding them all and then removing the unneeded bits. Signed-off-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Adrian Hunter authored
Now that sdhci_enable_irq_wakeups() is a local function, change it to return whether the IRQ wakeup was successfully enabled. This is in preparation for adding more conditions for whether IRQ wakeup is enabled. Note it is assumed, for SDHCI devices, that suspend is more important than wakeup, so we continue to suspend regardless. Signed-off-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Adrian Hunter authored
Now that it is not being used by any drivers, stop exporting it. Signed-off-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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- 11 Jan, 2018 1 commit
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Andy Shevchenko authored
On Intel Edison the Broadcom Wi-Fi card, which is connected to SDIO, requires 2.0v, while the host, according to Intel Merrifield TRM, supports 1.8v supply only. The card announces itself as mmc2: new ultra high speed DDR50 SDIO card at address 0001 Introduce a custom OCR mask for SDIO host controller on Intel Merrifield and add a special case to sdhci_set_power_noreg() to override 2.0v supply by enforcing 1.8v power choice. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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- 28 Nov, 2017 1 commit
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Ulf Hansson authored
The commit de3ee99b ("mmc: Delete bounce buffer handling") deletes the bounce buffer handling, but also causes the max_req_size for sdhci to be increased, in case when max_segs == 1. This causes errors for sdhci-pci Ricoh variant, about the swiotlb buffer to become full. Fix the issue, by taking IO_TLB_SEGSIZE and IO_TLB_SHIFT into account when deciding the max_req_size for sdhci. Reported-by:
Jiri Slaby <jslaby@suse.cz> Fixes: de3ee99b ("mmc: Delete bounce buffer handling") Cc: <stable@vger.kernel.org> # v4.14+ Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org> Tested-by:
Jiri Slaby <jslaby@suse.cz> Acked-by:
Adrian Hunter <adrian.hunter@intel.com>
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- 02 Nov, 2017 1 commit
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Kees Cook authored
In preparation for unconditionally passing the struct timer_list pointer to all timer callbacks, switch to using the new timer_setup() and from_timer() to pass the timer pointer explicitly. Cc: Ludovic Desroches <ludovic.desroches@microchip.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Carlo Caione <carlo@caione.org> Cc: Kevin Hilman <khilman@baylibre.com> Cc: Nicolas Pitre <nico@fluxnic.net> Cc: Jarkko Lavinen <jarkko.lavinen@nokia.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alex Dubov <oakad@yahoo.com> Cc: Bruce Chang <brucechang@via.com.tw> Cc: Harald Welte <HaraldWelte@viatech.com> Cc: Tony Olech <tony.olech@elandigitalsystems.com> Cc: Pierre Ossman <pierre@ossman.eu> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Paul Cercueil <paul@crapouillou.net> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Shawn Lin <shawn.lin@rock-chips.com> Cc: Arvind Yadav <arvind.yadav.cs@gmail.com> Cc: Allen <allen.lkml@gmail.com> Cc: linux-mmc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-amlogic@lists.infradead.org Cc: linux-omap@vger.kernel.org Cc: linux-usb@vger.kernel.org Signed-off-by:
Kees Cook <keescook@chromium.org> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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- 30 Oct, 2017 1 commit
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Wolfram Sang authored
Bail out everytime when mmc_regulator_get_supply() returns an errno, not only when probing gets deferred. This is currently a no-op, because this function only returns -EPROBE_DEFER or 0 right now. But if it will throw another error somewhen, it will be for a reason. (This still doesn't change that getting regulators is optional, so 0 can still mean no regulators found). So, let us a) be future proof and b) have driver code which is easier to understand. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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- 30 Aug, 2017 7 commits
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Kishon Vijay Abraham I authored
TI's implementation of sdhci controller used in DRA7 SoC's has CRC in responses with length 136 bits. Add quirk to indicate the controller has CRC in MMC_RSP_136. If this quirk is set sdhci library shouldn't shift the response present in SDHCI_RESPONSE register. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Adrian Hunter authored
Read each register only once and move the code to a separate function so that it is not jammed against the 80 column margin. Signed-off-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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yangbo lu authored
SD controller with SDHCI_QUIRK_NO_HISPD_BIT quirk probably use high speed enable bit for other purpose. So this bit shouldn't be changed for high speed enabling for this type of SD controller. Signed-off-by:
Yangbo Lu <yangbo.lu@nxp.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Michał Mirosław authored
Hosts supporting 8-bit bus are marked accordingly. If MMC_CAP_8_BIT_DATA is not among host capabilities, 8BITBUS bit will never be set and it is not cleared in case some non-SDHCI3 host uses it for something else. Signed-off-by:
Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Tested-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Srinivas Kandagatla authored
This patch adds sdma_boundary member to struct sdhci_host to give more flexibility to drivers to control the sdma boundary buffer value and also to fix issue on some sdhci controllers which are broken when HOST SDMA Buffer Boundary is programmed in Block Size Register (0x04) when using ADMA. Qualcomm sdhci controller is one of such type, writing to this bits is un-supported. Default value of sdma_boundary is set to SDHCI_DEFAULT_BOUNDARY_ARG. Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Zhoujie Wu authored
One issue was found on a removable high speed sd card with runtime pm enabled. When SD card is unplugged, it keep printing "Switching to 3.3V signalling voltage failed". And found below sequence triggers the error. mmc_rescan -> mmc_sd_detect -> mmc_power_off -- mmc->ios.vdd is updated to 0. -> mmc_claim_host -> sdhci_runtime_resume_host -> sdhci_start_signal_voltage_switch -> mmc_regulator_set_vqmmc -> mmc_ocrbitnum_to_vdd When mmc_ocrbitnum_to_vdd is called, the mmc->ios.vdd is 0, so it always return -EINVAL. The signal switch will always fail and print out warning. Ignore restoring the I/O state when runtime resume if MMC_POWER_OFF. Signed-off-by:
Zhoujie Wu <zjwu@marvell.com> Signed-off-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Shawn Lin authored
sdhci uses CONFIG_MMC_DEBUG for showing ADMA descriptor when occurring ADMA error. And it's also used to dump the registers whenever calling sdhci_add_host. On one hand, I don't see any burden to always print the state ADMA descriptor as it's rare and will help folks better understand what was happening when seeing ADMA error. On the other, folks may be interested in checking some registers at probe time. So we remove the sdhci_dumpregs from __sdhci_add_host and print some really useful registers in sdhci_setup_host. Suggested-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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- 24 Apr, 2017 4 commits
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Adrian Hunter authored
The delay between tuning commands for SD cards is not part of the specification. A driver that needs it probably needs it for eMMC too, whereas most drivers would probably like to set it to 0. Make it a host member (host->tuning_delay) that defaults to the existing behaviour. Drivers can set it to zero to eliminate the delay, or set it to a positive value to always have a delay. Signed-off-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Hu Ziji authored
Export sdhci_enable_sdio_irq() from sdhci.c. Thus vendor SDHC driver can implement its specific SDIO irq control. Signed-off-by:
Hu Ziji <huziji@marvell.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Hu Ziji authored
Export sdhci_start_signal_voltage_switch() from sdhci.c. Thus vendor sdhci driver can implement its own signal voltage switch routine. Signed-off-by:
Hu Ziji <huziji@marvell.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Hu Ziji authored
Export sdhci_set_ios() in sdhci.c. Thus vendor sdhci driver can implement its own set_ios() routine. Signed-off-by:
Hu Ziji <huziji@marvell.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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