- 07 Sep, 2023 4 commits
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Hamza Mahfooz authored
There are two places in apply_below_the_range() where it's possible for a divide by zero error to occur. So, to fix this make sure the divisor is non-zero before attempting the computation in both cases. Cc: stable@vger.kernel.org Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2637 Fixes: a463b263 ("drm/amd/display: Fix frames_to_insert math") Fixes: ded6119e ("drm/amd/display: Reinstate LFC optimization") Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Melissa Wen authored
For DRM legacy gamma, AMD display manager applies implicit sRGB degamma using a pre-defined sRGB transfer function. It works fine for DCN2 family where degamma ROM and custom curves go to the same color block. But, on DCN3+, degamma is split into two blocks: degamma ROM for pre-defined TFs and `gamma correction` for user/custom curves and degamma ROM settings doesn't apply to cursor plane. To get DRM legacy gamma working as expected, enable cursor degamma ROM for implict sRGB degamma on HW with this configuration. Cc: stable@vger.kernel.org Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2803 Fixes: 96b020e2 ("drm/amd/display: check attr flag before set cursor degamma on DCN3+") Signed-off-by:
Melissa Wen <mwen@igalia.com> Signed-off-by:
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Hamza Mahfooz authored
Since, calling dcn20_adjust_freesync_v_startup() on DCN3.1+ ASICs can cause the display to flicker and underflow to occur, we shouldn't call it for them. So, ensure that the DCN version is less than DCN_VERSION_3_1 before calling dcn20_adjust_freesync_v_startup(). Cc: stable@vger.kernel.org Reviewed-by:
Fangzhi Zuo <jerry.zuo@amd.com> Signed-off-by:
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Hamza Mahfooz authored
This reverts commit 3a31e8b8. We still need to call dcn20_adjust_freesync_v_startup() for older DCN3+ ASICs. Otherwise, it can cause DP to HDMI 2.1 PCONs to fail to light up. Cc: stable@vger.kernel.org Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2809Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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- 31 Aug, 2023 36 commits
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Christian König authored
The offset is just 32bits here so this can potentially overflow if somebody specifies a large value. Instead reduce the size to calculate the last possible offset. The error handling path incorrectly drops the reference to the user fence BO resulting in potential reference count underflow. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Hamza Mahfooz authored
This reverts commit e2066eb4. The problematic IGT test case (i.e. kms_atomic@plane-immutable-zpos) has been fixed as of commit cb77add45011 ("tests/kms_atomic: remove zpos < N-planes assert") to the IGT repo. So, reintroduce the reverted code. Link: https://gitlab.freedesktop.org/drm/igt-gpu-tools/-/commit/cb77add45011b129e21f3cb2a4089a73dde56179Acked-by:
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Jay Cornwall authored
mqd_stride function was introduced in commit 2f77b9a2 ("drm/amdkfd: Update MQD management on multi XCC setup") but not assigned for gfx11. Fixes a NULL dereference in debugfs. Signed-off-by:
Jay Cornwall <jay.cornwall@amd.com> Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Acked-by:
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Hawking Zhang authored
Do not access the pointer for ras input cmd buffer if it is even not allocated. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Stanley Yang <Stanley.Yang@amd.com> Signed-off-by:
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Rajneesh Bhardwaj authored
XCP partitions should not be visible for the VF for GFXIP 9.4.3. Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by:
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Tao Zhou authored
Instead of using direct update, avoid touching unrelated fields. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
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Alex Sierra authored
Interrupt sq data bits were not taken properly from contextid0 and contextid1. Use macro KFD_CONTEXT_ID_GET_SQ_INT_DATA instead. Signed-off-by:
Alex Sierra <alex.sierra@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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André Almeida authored
During a GPU reset, a normal memory reclaim could block to reclaim memory. Giving that coredump is a best effort mechanism, it shouldn't disturb the reset path. Change its memory allocation flag to a nonblocking one. Signed-off-by:
André Almeida <andrealmeid@igalia.com> Reviewed-by:
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Hawking Zhang authored
Driver queries umc_info v4_0 to identify ecc cap for aqua_vanjaram Signed-off-by:
Candice Li <candice.li@amd.com> Signed-off-by:
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Hawking Zhang authored
To be used by aqua_vanjaram Signed-off-by:
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Wenjing Liu authored
ODM power optimization is only supported with single stream. When ODM power optimization is enabled, we might not have enough free pipes for enabling other stream. So when we are committing more than 1 stream we should first switch off ODM power optimization to make room for new stream and then allocating pipe resource for the new stream. Cc: stable@vger.kernel.org Fixes: 59de751e ("drm/amd/display: add ODM case when looking for first split pipe") Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
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Gabe Teeger authored
[Why] We wait for mpc idle while in a locked state, leading to potential deadlock. [What] Move the wait_for_idle call to outside of HW lock. This and a call to wait_drr_doublebuffer_pending_clear are moved added to a new static helper function called wait_for_outstanding_hw_updates, to make the interface clearer. Cc: stable@vger.kernel.org Fixes: 8f0d304d ("drm/amd/display: Do not commit pipe when updating DRR") Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Gabe Teeger <gabe.teeger@amd.com> Signed-off-by:
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Wenjing Liu authored
When we are dynamically adding new ODM slices, we didn't update blank state, if the pipe used by new ODM slice is previously blanked, we will continue outputting blank pixel data on that slice causing right half of the screen showing blank image. The previous fix was a temporary hack to directly update current state when committing new state. This could potentially cause hw and sw state synchronization issues and it is not permitted by dc commit design. Cc: stable@vger.kernel.org Fixes: 7fbf451e ("drm/amd/display: Reinit DPG when exiting dynamic ODM") Reviewed-by:
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Fudong Wang authored
A benchmark stress test (12-40 machines x 48hours) found that DCN315 has cases where DC writes to an indirect register to set the smu clock msg id, but when we go to read the same indirect register the returned msg id doesn't match with what we just set it to. So, to fix this retry the write until the register's value matches with the requested value. Cc: stable@vger.kernel.org # 6.1+ Fixes: f9490399 ("drm/amd/display: Add DCN315 CLK_MGR") Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
Fudong Wang <fudong.wang@amd.com> Signed-off-by:
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Lijo Lazar authored
For APUs with SMU v13.0.6, mode-2 reset is kept as default and for others mode-1 is the default reset method. Signed-off-by:
Asad Kamal <asad.kamal@amd.com> Tested-by:
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Wenjing Liu authored
This partially reverts commit 460ea898 ("drm/amd/display: update add plane to context logic with a new algorithm"). The new secondary pipe allocation logic triggers an issue with a specific hardware state transition and causes a frame of corruption when toggling between windowed MPO and ODM desktop only mode. Ideally hwss is supposed to handle this scenario. We are temporarily reverting the logic and investigate the root cause why this transition would cause corruptions. Fixes: 460ea898 ("drm/amd/display: update add plane to context logic with a new algorithm") Reviewed-by:
Martin Leung <martin.leung@amd.com> Acked-by:
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Hamza Mahfooz authored
As made mention of in commit 099303e9 ("drm/amd/display: eDP intermittent black screen during PnP"), we need to turn off the display's backlight before powering off an eDP display. Not doing so will result in undefined behaviour according to the eDP spec. So, set DCN301's edp_backlight_control() function pointer to dce110_edp_backlight_control(). Cc: stable@vger.kernel.org Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2765 Fixes: 9c75891f ("drm/amd/display: rework recent update PHY state commit") Suggested-by:
Swapnil Patel <swapnil.patel@amd.com> Reviewed-by:
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Lijo Lazar authored
Implement the wait for bootloader call back for PSP v13.0 ASICs. Only for ASICs with PSP v13.0.6, it needs an additional check for VBIOS mailbox status. Signed-off-by:
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Hamza Mahfooz authored
fbcon requires that we implement &drm_framebuffer_funcs.dirty. Otherwise, the framebuffer might take a while to flush (which would manifest as noticeable lag). However, we can't enable this callback for non-fbcon cases since it may cause too many atomic commits to be made at once. So, implement amdgpu_dirtyfb() and only enable it for fbcon framebuffers (we can use the "struct drm_file file" parameter in the callback to check for this since it is only NULL when called by fbcon, at least in the mainline kernel) on devices that support atomic KMS. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: stable@vger.kernel.org # 6.1+ Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2519Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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Mangesh Gadre authored
Update TCP/UTCL1 thrashing control settings v2: updated rev_id check Signed-off-by:
Mangesh Gadre <Mangesh.Gadre@amd.com> Reviewed-by:
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Alex Deucher authored
Print both input and avg power. Fixes: 47f1724d ("drm/amd: Introduce `AMDGPU_PP_SENSOR_GPU_INPUT_POWER`") Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Hawking Zhang authored
amdgpu_device_mode1_reset will return gpu mode1_reset succeed (ret = 0) as long as wait_for_bootloader call succeed, regardless of the status reported by smu or psp firmware. This results to driver continue executing recovery even smu or psp fail to perform mode1 reset. Signed-off-by:
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SungHuai Wang authored
[WHY] OTG_STATIC_SCREEN_EVENT_MASK is changed in DCN3, but we still follow DCN2 to apply setting for OTG_STATIC_SCREEN_EVENT_MASK. [How] Add new function to apply correct settings for DCN3 series. Reviewed-by:
Anthony Koo <anthony.koo@amd.com> Acked-by:
Wayne Lin <wayne.lin@amd.com> Signed-off-by:
SungHuai Wang <danny.wang@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Hamza Mahfooz authored
As made mention of in commit 4a2df0d1 ("drm/amd/display: Fixed non-native modes not lighting up"), we shouldn't call drm_mode_set_crtcinfo() once the crtc timings have been decided. Since, it can cause settings to be unintentionally overwritten. So, since dm_state is never NULL now, we can use old_stream to determine if we should call drm_mode_set_crtcinfo() because we only need to set the crtc timing parameters for entirely new streams. Cc: Harry Wentland <harry.wentland@amd.com> Cc: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Fixes: bd49f190 ("drm/amd/display: Always set crtcinfo from create_stream_for_sink") Reviewed-by:
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Asad Kamal authored
Critical Temperature needs to be reported in millidegree Celsius. Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
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Mangesh Gadre authored
rlc firmware does required setting, driver need not do it. Signed-off-by:
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Lijo Lazar authored
Add a function to wait till bootloader has reached steady state. Signed-off-by:
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Horace Chen authored
[What] Current SRIOV still using adev->clock.default_XX which gets from atomfirmware. But these fields are abandoned in atomfirmware long ago. Which may cause function to return a 0 value. [How] We don't need to check whether SR-IOV. For SR-IOV one-vf-mode, pm is enabled and VF is able to read dpm clock from pmfw, so we can use dpm clock interface directly. For multi-VF mode, VF pm is disabled, so driver can just react as pm disabled. One-vf-mode is introduced from GFX9 so it shall not have any backward compatibility issue. Signed-off-by:
Horace Chen <horace.chen@amd.com> Acked-by:
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Lijo Lazar authored
BACO dummy mode could be set under reset conditions and that affects framebuffer access. Check If baco dummy mode is set, unset it if so. Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
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ChunTao Tso authored
[Why] If VBlank_nom is too small, it will cause VStartUP_Start smaller than VBackPorch + VSync width which is an invalid case for VStartUP_Start and where to send AS-SDP. [How] Setup a minimum value to VBlank_nom Reviewed-by:
Reza Amini <reza.amini@amd.com> Acked-by:
ChunTao Tso <chuntao.tso@amd.com> Tested-by:
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Reza Amini authored
[why] vstartup is calculated to be a large number. it works because it is within vertical blank, but it reduces region of blank that can be used for power gating. [how] Calculation needs to convert micro seconds to number of vertical lines. Reviewed-by:
Kazlauskas Nicholas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Ovidiu Bunea authored
[why] This Unit correction exposes a Replay corruption. [how] This reverts commit: commit dbd29029 ("drm/amd/display: Correct unit conversion for vstartup") Roll back unit conversion until Replay can fix their corruption. Fixes: dbd29029 ("drm/amd/display: Correct unit conversion for vstartup") Reviewed-by:
Ovidiu Bunea <ovidiu.bunea@amd.com> Tested-by:
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YiPeng Chai authored
Enable ras for mp0 v13_0_6 sriov Signed-off-by:
YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by:
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Alex Sierra authored
if hmm_range_get_pages returns EBUSY error during svm_range_validate_and_map, within the context of a page fault interrupt. This should retry through svm_range_restore_pages callback. Therefore we treat this as EAGAIN error instead, and defer it to restore pages fallback. Signed-off-by:
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Samir Dhume authored
Powergating is handled in the host driver. Reviewed-by:
Zhigang Luo <zhigang.luo@amd.com> Signed-off-by:
Samir Dhume <samir.dhume@amd.com> Signed-off-by:
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Asad Kamal authored
Add critical temperature message support func for smu v13.0.6 and expose critical temperature as part of hw mon attributes for GC v9.4.3 v2: Added comment for pmfw version requirement & move the check to get_thermal_temperature_range function Signed-off-by:
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