- 13 Jul, 2018 11 commits
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Andrey Grodzovsky authored
v2: Rebase v3: Use defines for CP_SQ and CP_ECC_ERROR interrupts. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
Stop using 'magic numbers' when registering interrupt sources. v2: Clean redundant comments. Switch to kernel style comments. v3: Add CP_ECC_ERROR define Signed-off-by:
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Evan Quan authored
Convert the clocks into right Mhz unit. Otherwise, it will miss the equal situation. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Evan Quan authored
Gfxoff feature for vega12 is workable. So, there is no need to mask it any more. Signed-off-by:
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Evan Quan authored
Export apis for enabling/disabling SMU gfxoff support. v2: fit the latest gfxoff support framework v3: add feature_mask control Signed-off-by:
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Evan Quan authored
Gfxoff feature may depends on the CGCG(on vega12, that's the case). This change will help to enable gfxoff feature more frequently. Signed-off-by:
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Evan Quan authored
On vega12, the bit0 of RLC_CGTT_MGCG_OVERRIDE is reserved. Signed-off-by:
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Evan Quan authored
SMU owns this register so the driver should not set it to avoid breaking gfxoff. v2: update description Signed-off-by:
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Evan Quan authored
The save restore list initialization does not have to be pg guarded. And for some asic(e.g. Vega12), it does not have cntl/gpm/srm lists. Signed-off-by:
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Evan Quan authored
CSIB init has no relation with rlc version and pg status. It should be needed regardless of them. Signed-off-by:
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Evan Quan authored
Without this pin, the csb buffer will be filled with inconsistent data after S3 resume. And that will causes gfx hang on gfxoff exit since this csb will be executed then. v2: fit amdgpu_bo_pin change(take one less argument) Signed-off-by:
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- 10 Jul, 2018 25 commits
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kbuild test robot authored
drivers/gpu/drm/amd/amdgpu/../powerplay/amd_powerplay.c:1209:17-18: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Fixes: ea870e44 ("drm/amd/pp: Export notify_smu_enable_pwe to display") CC: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
kbuild test robot <fengguang.wu@intel.com> Signed-off-by:
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Leo Liu authored
Fixes: 22cc6c5e (drm/amdgpu: Add runtime VCN PG support) Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
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Leo Liu authored
To make register read/write reliable Signed-off-by:
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Leo Liu authored
VCN won't get power off when only jpeg active Signed-off-by:
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Thomas Zimmermann authored
A call to ttm_bo_unref() clears the supplied pointer to NULL, while ttm_bo_put() does not. None of the converted call sites requires the pointer to become NULL, so the respective assign operations has been left out from the patch. Signed-off-by:
Thomas Zimmermann <contact@tzimmermann.org> Reviewed-by:
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Thomas Zimmermann authored
Signed-off-by:
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Thomas Zimmermann authored
The TTM buffer-object interface provides ttm_bo_reference() and ttm_bo_unref() for managing reference counts. Replacing them with ttm_bo_get() and ttm_bo_put() aligns the API with conventions used throughout the Linux kernel. The implementation of ttm_bo_unref() clears the supplied pointer to NULL. This leads to workarounds where the caller saves the pointer's value before de-referencing the BO. ttm_bo_put() does not clear the supplied pointer. Signed-off-by:
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Gustavo A. R. Silva authored
Make use of the swap macro and remove unnecessary variable *tmp_mem*. This makes the code easier to read and maintain. Also, reduces the stack usage. This code was detected with the help of Coccinelle. Signed-off-by:
Gustavo A. R. Silva <gustavo@embeddedor.com> Reviewed-by:
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Harry Wentland authored
The previous change wasn't covering smu 7 and 8 and therefore DC was seeing wrong clock values. This fixes an issue where the pipes seem to hang with a 4k DP and 1080p HDMI display. Fixes: c3df50abc84b ("drm/amd/pp: Convert clock unit to KHz as defined") Signed-off-by:Harry Wentland <harry.wentland@amd.com> Acked-by:
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Andrey Grodzovsky authored
Problem: When PD/PT update made by CPU root PD was not yet mapped causing page fault. Fix: Verify root PD is mapped into CPU address space. v2: Make sure that we add the root PD to the relocated list since then it's get mapped into CPU address space bt default in amdgpu_vm_update_directories. v3: Drop change to not move kernel type BOs to evicted list. v4: Remove redundant bo move to relocated list. Link: https://bugs.freedesktop.org/show_bug.cgi?id=107065Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
Extract and present the reposnsible process and thread when VM_FAULT happens. v2: Use getter and setter functions. Signed-off-by:
Jim Qu <Jim.Qu@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
Add process and thread names and pids and a function to extract this info from relevant amdgpu_vm. v2: Add documentation and fix identation. v3: Add getter and setter functions for amdgpu_task_info. Signed-off-by:
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Harry Wentland authored
const to avoid hard-to-find bugs where some function overrides a function pointer. Signed-off-by:
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Christian König authored
It is good practice to make global function tables const to avoid accidental override. Signed-off-by:
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Christian König authored
Otherwise we try to program hardware with the wrong watermark functions when multiple DCE generations are installed in one system. Signed-off-by:
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Rex Zhu authored
The default clock unit in powerplay is 10KHz. Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Rex Zhu authored
so we can read/write the registers in CLK domain through RREG32/WREG32_SOC15 Reviewed-by:
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Michel Dänzer authored
Without this, there could not be enough slots, which could trigger the BUG_ON in reservation_object_add_shared_fence. v2: * Jump to the error label instead of returning directly (Jerry Zhang) v3: * Reserve slots for command submission after VM updates (Christian König) Cc: stable@vger.kernel.org Bugzilla: https://bugs.freedesktop.org/106418 Reported-by: mikhail.v.gavrilov@gmail.com Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Junwei Zhang authored
kmap happens after bo pin, so unpin is required on error Signed-off-by:
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Junwei Zhang authored
Instead of calling gart address space on every bo pin, allocates it on demand v2: fix error handling v3: drop the change on amdgpu_amdkfd_gpuvm.c, not needed. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
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Junwei Zhang authored
It could be got by amdgpu_bo_gpu_offset() if need Signed-off-by:
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git://people.freedesktop.org/~thomash/linuxDave Airlie authored
This introduces a header update and support for multisample surfaces. Signed-off-by:
Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/d020efb8-776d-5e8f-9d9f-122591e074d6@vmware.com
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git://people.freedesktop.org/~thomash/linuxDave Airlie authored
A series of cleanups / reorganizations and modesetting changes that mostly target atomic state validation. [airlied: conflicts with SPDX stuff in amdgpu tree] Signed-off-by:
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
More features for 4.19: - Use core pcie functionality rather than duplicating our own for pcie gens and lanes - Scheduler function naming cleanups - More documentation - Reworked DC/Powerplay interfaces to improve power savings - Initial stutter mode support for RV (power feature) - Vega12 powerplay updates - GFXOFF fixes - Misc fixes Signed-off-by:
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https://github.com/jsarha/linuxDave Airlie authored
tilcdc pull request for v4.19 Single fix to defer probing. Signed-off-by:
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- 06 Jul, 2018 4 commits
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Deepak Rawat authored
A new param DRM_VMW_PARAM_SM4_1, is added for user space to determine availability of SM4.1. Minor version bump for SM4.1. Signed-off-by:
Deepak Rawat <drawat@vmware.com> Reviewed-by:
Sinclair Yeh <syeh@vmware.com> Reviewed-by:
Brian Paul <brianp@vmware.com> Reviewed-by:
Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by:
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Deepak Rawat authored
Support for SVGA3D_SURFACE_MULTISAMPLE and surface mob size according to sample count. Signed-off-by:
Charmaine Lee <charmainel@vmware.com> Signed-off-by:
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Deepak Rawat authored
New ioctls DRM_VMW_GB_SURFACE_CREATE_EXT and DRM_VMW_GB_SURFACE_REF_EXT are added which support 64-bit wide svga device surface flags, quality level and multisample pattern. Signed-off-by:
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Deepak Rawat authored
Since svga device introduced new 64bit SVGA3dSurfaceAllFlags, vmwgfx now stores the surface flags internally as SVGA3dSurfaceAllFlags. For legacy surface define commands, only lower 32-bit is used. Signed-off-by:
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