1. 10 Mar, 2022 1 commit
    • Takashi Iwai's avatar
      Merge tag 'asoc-fix-v5.17-rc7' of... · 09354ebe
      Takashi Iwai authored
      Merge tag 'asoc-fix-v5.17-rc7' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus
      
      ASoC: Potential fixes for v5.17
      
      Rather more fixes here than I'm comfortable with, we've had several
      vendors noticing issues late in the release cycle all of which are valid
      and reasonable fixes but it adds up to a much larger change set than I'd
      like.  Several of the AMD fixes look like cleanups from the subject
      lines but are actually fixing user visible problems as well.
      
      If you were to merge this for 5.18 rather than 5.17 it wouldn't be the
      end of the world, stable will probably backport everything anyway.
      09354ebe
  2. 08 Mar, 2022 1 commit
  3. 07 Mar, 2022 3 commits
  4. 05 Mar, 2022 2 commits
  5. 04 Mar, 2022 1 commit
    • Takashi Sakamoto's avatar
      ALSA: firewire-lib: fix uninitialized flag for AV/C deferred transaction · bf0cd60b
      Takashi Sakamoto authored
      AV/C deferred transaction was supported at a commit 00a7bb81 ("ALSA:
      firewire-lib: Add support for deferred transaction") while 'deferrable'
      flag can be uninitialized for non-control/notify AV/C transactions.
      UBSAN reports it:
      
      kernel: ================================================================================
      kernel: UBSAN: invalid-load in /build/linux-aa0B4d/linux-5.15.0/sound/firewire/fcp.c:363:9
      kernel: load of value 158 is not a valid value for type '_Bool'
      kernel: CPU: 3 PID: 182227 Comm: irq/35-firewire Tainted: P           OE     5.15.0-18-generic #18-Ubuntu
      kernel: Hardware name: Gigabyte Technology Co., Ltd. AX370-Gaming 5/AX370-Gaming 5, BIOS F42b 08/01/2019
      kernel: Call Trace:
      kernel:  <IRQ>
      kernel:  show_stack+0x52/0x58
      kernel:  dump_stack_lvl+0x4a/0x5f
      kernel:  dump_stack+0x10/0x12
      kernel:  ubsan_epilogue+0x9/0x45
      kernel:  __ubsan_handle_load_invalid_value.cold+0x44/0x49
      kernel:  fcp_response.part.0.cold+0x1a/0x2b [snd_firewire_lib]
      kernel:  fcp_response+0x28/0x30 [snd_firewire_lib]
      kernel:  fw_core_handle_request+0x230/0x3d0 [firewire_core]
      kernel:  handle_ar_packet+0x1d9/0x200 [firewire_ohci]
      kernel:  ? handle_ar_packet+0x1d9/0x200 [firewire_ohci]
      kernel:  ? transmit_complete_callback+0x9f/0x120 [firewire_core]
      kernel:  ar_context_tasklet+0xa8/0x2e0 [firewire_ohci]
      kernel:  tasklet_action_common.constprop.0+0xea/0xf0
      kernel:  tasklet_action+0x22/0x30
      kernel:  __do_softirq+0xd9/0x2e3
      kernel:  ? irq_finalize_oneshot.part.0+0xf0/0xf0
      kernel:  do_softirq+0x75/0xa0
      kernel:  </IRQ>
      kernel:  <TASK>
      kernel:  __local_bh_enable_ip+0x50/0x60
      kernel:  irq_forced_thread_fn+0x7e/0x90
      kernel:  irq_thread+0xba/0x190
      kernel:  ? irq_thread_fn+0x60/0x60
      kernel:  kthread+0x11e/0x140
      kernel:  ? irq_thread_check_affinity+0xf0/0xf0
      kernel:  ? set_kthread_struct+0x50/0x50
      kernel:  ret_from_fork+0x22/0x30
      kernel:  </TASK>
      kernel: ================================================================================
      
      This commit fixes the bug. The bug has no disadvantage for the non-
      control/notify AV/C transactions since the flag has an effect for AV/C
      response with INTERIM (0x0f) status which is not used for the transactions
      in AV/C general specification.
      
      Fixes: 00a7bb81 ("ALSA: firewire-lib: Add support for deferred transaction")
      Signed-off-by: default avatarTakashi Sakamoto <o-takashi@sakamocchi.jp>
      Link: https://lore.kernel.org/r/20220304125647.78430-1-o-takashi@sakamocchi.jpSigned-off-by: default avatarTakashi Iwai <tiwai@suse.de>
      bf0cd60b
  6. 02 Mar, 2022 1 commit
  7. 24 Feb, 2022 9 commits
  8. 23 Feb, 2022 8 commits
  9. 17 Feb, 2022 3 commits
  10. 16 Feb, 2022 2 commits
  11. 14 Feb, 2022 7 commits
  12. 10 Feb, 2022 2 commits
    • Charles Keepax's avatar
      ASoC: wm_adsp: Correct control read size when parsing compressed buffer · a887f9c7
      Charles Keepax authored
      When parsing the compressed stream the whole buffer descriptor is
      now read in a single cs_dsp_coeff_read_ctrl; on older firmwares
      this descriptor is just 4 bytes but on more modern firmwares it is
      24 bytes. The current code reads the full 24 bytes regardless, this
      was working but reading junk for the last 20 bytes. However commit
      f444da38 ("firmware: cs_dsp: Add offset to cs_dsp read/write")
      added a size check into cs_dsp_coeff_read_ctrl, causing the older
      firmwares to now return an error.
      
      Update the code to only read the amount of data appropriate for
      the firmware loaded.
      
      Fixes: 04ae0859 ("ASoC: wm_adsp: Switch to using wm_coeff_read_ctrl for compressed buffers")
      Signed-off-by: default avatarCharles Keepax <ckeepax@opensource.cirrus.com>
      Link: https://lore.kernel.org/r/20220210172053.22782-1-ckeepax@opensource.cirrus.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      a887f9c7
    • Stephen Boyd's avatar
      ASoC: qcom: Actually clear DMA interrupt register for HDMI · c8d251f5
      Stephen Boyd authored
      In commit da0363f7 ("ASoC: qcom: Fix for DMA interrupt clear reg
      overwriting") we changed regmap_write() to regmap_update_bits() so that
      we can avoid overwriting bits that we didn't intend to modify.
      Unfortunately this change breaks the case where a register is writable
      but not readable, which is exactly how the HDMI irq clear register is
      designed (grep around LPASS_HDMITX_APP_IRQCLEAR_REG to see how it's
      write only). That's because regmap_update_bits() tries to read the
      register from the hardware and if it isn't readable it looks in the
      regmap cache to see what was written there last time to compare against
      what we want to write there. Eventually, we're unable to modify this
      register at all because the bits that we're trying to set are already
      set in the cache.
      
      This is doubly bad for the irq clear register because you have to write
      the bit to clear an interrupt. Given the irq is level triggered, we see
      an interrupt storm upon plugging in an HDMI cable and starting audio
      playback. The irq storm is so great that performance degrades
      significantly, leading to CPU soft lockups.
      
      Fix it by using regmap_write_bits() so that we really do write the bits
      in the clear register that we want to. This brings the number of irqs
      handled by lpass_dma_interrupt_handler() down from ~150k/sec to ~10/sec.
      
      Fixes: da0363f7 ("ASoC: qcom: Fix for DMA interrupt clear reg overwriting")
      Cc: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
      Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
      Signed-off-by: default avatarStephen Boyd <swboyd@chromium.org>
      Link: https://lore.kernel.org/r/20220209232520.4017634-1-swboyd@chromium.orgSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      c8d251f5