- 12 Feb, 2024 22 commits
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Eugen Hristev authored
The larb clock is in fact a subsys clock, so it must be prefixed by 'subsys-' to be correctly identified in the driver. Fixes: d9e43c1e ("arm64: dts: mt8186: Add power domains controller") Signed-off-by:
Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20231228113245.174706-6-eugen.hristev@collabora.comSigned-off-by:
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Eugen Hristev authored
Add compatible for the mt8186 encoder which currently works in the same way as mt8183. Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
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Eugen Hristev authored
Clock name should be `venc_sel` as per binding. Fix the warning message : arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dtb: vcodec@17020000: clock-names:0: 'venc_sel' was expected from schema $id: http://devicetree.org/schemas/media/mediatek,vcodec-encoder.yaml# Fixes: aa8f3711 ("arm64: dts: mt8192: Add H264 venc device node") Signed-off-by: -
Eugen Hristev authored
Looking at the binding it makes sense that the `-vp8` compatible has the `venc_lt_sel` while the other bindings have the `venc_sel` as name for the clock. This was also mentioned in the txt version of the binding before the conversion: ` clock-names: avc encoder must contain "venc_sel", vp8 encoder must contain "venc_lt_sel", decoder must contain "vcodecpll", "univpll_d2", ` So it is easier to check for compatible that includes vp8, since that's just one, to have the requirement for the clock name property as `venc_lt_sel`, rather than for all the others, some of which are missing, thus for them, the requirement is wrongly `venc_lt_sel`. Reordered the if/then/else to match `-vp8` and have all the rest of the compatibles using the other clock name (`venc_sel`). Signed-off-by:
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William-tw Lin authored
Add efuse nodes for socinfo retrieval for MT8173, MT8183, MT8186, MT8192 and MT8195. Signed-off-by:
William-tw Lin <william-tw.lin@mediatek.com> Reviewed-by:
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Mark Hasemeyer authored
The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Signed-off-by:
Mark Hasemeyer <markhas@chromium.org> Reviewed-by:
Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by:
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Mark Hasemeyer authored
The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Signed-off-by:
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Mark Hasemeyer authored
The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Signed-off-by:
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Mark Hasemeyer authored
The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Signed-off-by:
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Rafał Miłecki authored
Add bindings of on-SoC clocks. Signed-off-by:
Rafał Miłecki <rafal@milecki.pl> Reviewed-by:
Daniel Golle <daniel@makrotopia.org> Link: https://lore.kernel.org/r/20240108085228.4727-4-zajec5@gmail.comSigned-off-by:
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Rafał Miłecki authored
MT7988A (AKA MediaTek Filogic 880) is a quad-core ARM Cortex-A73 platform designed for Wi-Fi 7 devices (there is no wireless on SoC though). The first public MT7988A device is Banana Pi BPI-R4. Many SoC parts remain to be added (they need their own bindings or depend on missing clocks). Those present block however are correct and having base .dtsi will help testing & working on missing stuff. Signed-off-by:
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Rafał Miłecki authored
MT7988A is another MediaTek's SoC with just 1 device available right now: Banana Pi BPI-R4. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240108085228.4727-2-zajec5@gmail.comSigned-off-by:
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Rafał Miłecki authored
MT7981B (AKA MediaTek Filogic 820) is a dual-core ARM Cortex-A53 SoC. One of market devices using this SoC is Xiaomi AX3000T. This is initial contribution with basic SoC support. More hardware block will get added later. Some will need their bindings (like auxadc). Signed-off-by:
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Rafał Miłecki authored
MT7981B (AKA Filogic 820) is MediaTek's dual-core ARM Cortex-A53 SoC. One of market devices using this SoC is Xiaomi AX3000T. Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240111103928.721-2-zajec5@gmail.comSigned-off-by:
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Nícolas F. R. A. Prado authored
The commit adding the ChromeOS EC to the Asurada Devicetree mistakenly added a base detection node. While tablet mode detection is supported by CrosEC and used by Hayato, it is done through the cros-ec-keyb driver. The base detection node, which is handled by the hid-google-hammer driver, also provides tablet mode detection but by checking base attachment status on the CrosEC, which is not supported for Asurada. Hence, remove the unused CrosEC base detection node for Asurada. Fixes: eb188a2a ("arm64: dts: mediatek: asurada: Add ChromeOS EC") Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20240207-mt8192-asurada-cbas-remove-v1-1-04cb65951975@collabora.comSigned-off-by:
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Rafał Miłecki authored
MT7986's Infrastructure System Configuration Controller includes reset controller. It can reset blocks as specified in the include/dt-bindings/reset/mt7986-resets.h . Add #reset-cells so it can be referenced properly. This fixes: arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtb: infracfg@10001000: '#reset-cells' is a required property from schema $id: http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml# Fixes: 1f9986b2 ("arm64: dts: mediatek: add clock support for mt7986a") Cc: Sam Shih <sam.shih@mediatek.com> Signed-off-by: -
Rafał Miłecki authored
PWM is not a clock provider and its binding doesn't specify "#clock-cells" property. This fixes: arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtb: pwm@10048000: '#clock-cells' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/pwm/mediatek,mt2712-pwm.yaml# Fixes: eabb04df ("arm64: dts: mt7986: add PWM") Cc: Daniel Golle <daniel@makrotopia.org> Signed-off-by: -
Rafał Miłecki authored
This fixes following validation errors: arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtb: spi_nand@0: $nodename:0: 'spi_nand@0' does not match '^(flash|.*sram|nand)(@.*)?$' from schema $id: http://devicetree.org/schemas/mtd/spi-nand.yaml# arch/arm64/boot/dts/mediatek/mt7986b-rfb.dtb: spi_nand@0: $nodename:0: 'spi_nand@0' does not match '^(flash|.*sram|nand)(@.*)?$' from schema $id: http://devicetree.org/schemas/mtd/spi-nand.yaml# Fixes: 885e153e ("arm64: dts: mt7986: add spi related device nodes") Signed-off-by: -
Rafał Miłecki authored
This fixes SPI setup and resolves following validation errors: arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtb: spi_nand@0: Unevaluated properties are not allowed ('spi-rx-buswidth', 'spi-tx-buswidth' were unexpected) from schema $id: http://devicetree.org/schemas/mtd/spi-nand.yaml# arch/arm64/boot/dts/mediatek/mt7986b-rfb.dtb: spi_nand@0: Unevaluated properties are not allowed ('spi-rx-buswidth', 'spi-tx-buswidth' were unexpected) from schema $id: http://devicetree.org/schemas/mtd/spi-nand.yaml# Fixes: 885e153e ("arm64: dts: mt7986: add spi related device nodes") Signed-off-by: -
Rafał Miłecki authored
According to the "inside-secure,safexcel-eip97" binding "clock-names" is required only if there are two clocks specified. If present the first name must by "core". Name "infra_eip97_ck" is invalid and was probably just a typo. Drop it. Fixes: ecc5287c ("arm64: dts: mt7986: add crypto related device nodes") Cc: Sam Shih <sam.shih@mediatek.com> Signed-off-by:
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Rafał Miłecki authored
This fixes typo and resolves following validation error: arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtb: pwm-fan: pwms: [[54, 0, 10000], [0]] is too long from schema $id: http://devicetree.org/schemas/hwmon/pwm-fan.yaml# Fixes: c26f779a ("arm64: dts: mt7986: add pwm-fan and cooling-maps to BPI-R3 dts") Cc: Daniel Golle <daniel@makrotopia.org> Signed-off-by: -
Nícolas F. R. A. Prado authored
The cbas node is used to describe base detection functionality in the ChromeOS EC, which is used for units that have a detachable keyboard and thus rely on this functionality to switch between tablet and laptop mode. Despite the original commit having added the cbas node to the mt8183-kukui.dtsi, not all machines that include it are detachables. In fact all machines that include from mt8183-kukui-jacuzzi.dtsi are either clamshells (ie normal laptops) or convertibles, meaning the keyboard can be flipped but not detached. The detection for the keyboard getting flipped is handled by the driver bound to the keyboard-controller node in the EC. Move the base detection node from the base kukui dtsi to the dtsis where all machines are detachables, and thus actually make use of the node. Fixes: 4fa8492d ("arm64: dts: mt8183: add cbas node under cros_ec") Signed-off-by:
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- 21 Jan, 2024 18 commits
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Linus Torvalds authored
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https://evilpiepirate.org/git/bcachefsLinus Torvalds authored
Pull more bcachefs updates from Kent Overstreet: "Some fixes, Some refactoring, some minor features: - Assorted prep work for disk space accounting rewrite - BTREE_TRIGGER_ATOMIC: after combining our trigger callbacks, this makes our trigger context more explicit - A few fixes to avoid excessive transaction restarts on multithreaded workloads: fstests (in addition to ktest tests) are now checking slowpath counters, and that's shaking out a few bugs - Assorted tracepoint improvements - Starting to break up bcachefs_format.h and move on disk types so they're with the code they belong to; this will make room to start documenting the on disk format better. - A few minor fixes" * tag 'bcachefs-2024-01-21' of https://evilpiepirate.org/git/bcachefs: (46 commits) bcachefs: Improve inode_to_text() bcachefs: logged_ops_format.h bcachefs: reflink_format.h bcachefs; extents_format.h bcachefs: ec_format.h bcachefs: subvolume_format.h bcachefs: snapshot_format.h bcachefs: alloc_background_format.h bcachefs: xattr_format.h bcachefs: dirent_format.h bcachefs: inode_format.h bcachefs; quota_format.h bcachefs: sb-counters_format.h bcachefs: counters.c -> sb-counters.c bcachefs: comment bch_subvolume bcachefs: bch_snapshot::btime bcachefs: add missing __GFP_NOWARN bcachefs: opts->compression can now also be applied in the background bcachefs: Prep work for variable size btree node buffers bcachefs: grab s_umount only if snapshotting ... -
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull timer updates from Thomas Gleixner: "Updates for time and clocksources: - A fix for the idle and iowait time accounting vs CPU hotplug. The time is reset on CPU hotplug which makes the accumulated systemwide time jump backwards. - Assorted fixes and improvements for clocksource/event drivers" * tag 'timers-core-2024-01-21' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: tick-sched: Fix idle and iowait sleeptime accounting vs CPU hotplug clocksource/drivers/ep93xx: Fix error handling during probe clocksource/drivers/cadence-ttc: Fix some kernel-doc warnings clocksource/drivers/timer-ti-dm: Fix make W=n kerneldoc warnings clocksource/timer-riscv: Add riscv_clock_shutdown callback dt-bindings: timer: Add StarFive JH8100 clint dt-bindings: timer: thead,c900-aclint-mtimer: separate mtime and mtimecmp regs -
git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linuxLinus Torvalds authored
Pull powerpc fixes from Aneesh Kumar: - Increase default stack size to 32KB for Book3S Thanks to Michael Ellerman. * tag 'powerpc-6.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: powerpc/64s: Increase default stack size to 32KB
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Kent Overstreet authored
Add line breaks - inode_to_text() is now much easier to read. Signed-off-by:Kent Overstreet <kent.overstreet@linux.dev>
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Kent Overstreet authored
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Kent Overstreet authored
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Kent Overstreet authored
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Kent Overstreet authored
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Kent Overstreet authored
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Kent Overstreet authored
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Kent Overstreet authored
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Kent Overstreet authored
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Kent Overstreet authored
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Kent Overstreet authored
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Kent Overstreet authored
Signed-off-by: -
Kent Overstreet authored
bcachefs_format.h has gotten too big; let's do some organizing. Signed-off-by: -
Kent Overstreet authored
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