1. 18 Aug, 2014 4 commits
    • Bill Pringlemeir's avatar
      ARM: dts: vf610-twr: Fix pinctrl_esdhc1 pin definitions. · 0aa4dcb5
      Bill Pringlemeir authored
      Previous version had an extra 'fsl' which made the pins not match
      any entry.  The console message,
      
       vf610-pinctrl 40048000.iomuxc: no fsl,pins property in node \
          /soc/aips-bus@40000000/iomuxc@40048000/vf610-twr/esdhc1grp
      
      is displayed without the fix.  The prior version would generally
      work as u-boot sets the pins properly for sdhc.  This change allows
      Linux sdhc use even if u-boot is built without sdhc support.
      Signed-off-by: default avatarBill Pringlemeir <bpringlemeir@nbsps.com>
      Acked-by: default avatarStefan Agner <stefan@agner.ch>
      Fixes: 0517fe6a ("ARM: dts: vf610-twr: Add support for sdhc1")
      Cc: <stable@vger.kernel.org>
      Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
      0aa4dcb5
    • Shawn Guo's avatar
      ARM: imx: remove unnecessary ARCH_HAS_OPP select · df216074
      Shawn Guo authored
      Since ARCH_MXC already selects ARCH_HAS_OPP, it's really unnecessary for
      SOC_IMX27 and SOC_IMX5 to select it again.
      Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
      df216074
    • Shawn Guo's avatar
      ARM: imx: fix TLB missing of IOMUXC base address during suspend · 59d05b51
      Shawn Guo authored
      After the suspend routine running in OCRAM puts DDR into self-refresh,
      it will access IOMUXC block to float DDR IO for power saving.  A TLB
      missing of IOMUXC base address may happen in this case, and triggers an
      access to DDR, and thus hangs the system.
      
      The failure is discovered by running suspend/resume on a Cubox-i board.
      Though the issue is not Cubox-i specific, it can be hit the on the board
      quite easily with the 3.15 or 3.16 kernel.
      
      Fix the issue with a dummy access to IOMUXC block at the beginning of
      suspend routine, so that the address translation can be filled into TLB
      before DDR is put into self-refresh.
      Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
      Cc: <stable@vger.kernel.org>
      Acked-by: default avatarAnson Huang <Anson.Huang@freescale.com>
      59d05b51
    • Arnd Bergmann's avatar
      ARM: imx6: fix SMP compilation again · 060d517d
      Arnd Bergmann authored
      My earlier patch 1fc593fe ("ARM: imx: build i.MX6 functions
      only when needed") fixed a problem with building an i.MX5 kernel,
      but now the problem has returned for the case where we allow
      ARMv6K SMP builds in multiplatform. With CONFIG_CPU_V7 disabled,
      but i.MX3 and SMP enabled, we get this build error:
      
      arch/arm/mach-imx/built-in.o: In function `v7_secondary_startup':
      :(.text+0x5124): undefined reference to `v7_invalidate_l1'
      
      This puts the code inside of an "ifdef CONFIG_SOC_IMX6" to hopefully
      do the right thing in all configurations.
      Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
      Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
      060d517d
  2. 16 Aug, 2014 36 commits