- 25 Jul, 2023 23 commits
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Ovidiu Bunea authored
[Why] In some vendor specific retimer setups for downstream 4-lane HBR3 configuration, the sink will show severe corruption (horizontal shifting) and intermittent blanking. [How] Add new retimer programming sequence before clock recovery when 4 lanes are active. Reviewed-by:
Michael Strauss <michael.strauss@amd.com> Acked-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
Ovidiu Bunea <ovidiu.bunea@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Wenjing Liu authored
[Why] Last ODM slice could be slightly larger than other slice because it can be including the residual. [How] Update DPG pattern programming sequence to use a different width for last odm slice. Reviewed-by:
Chris Park <chris.park@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Reza Amini authored
[Why] vstartup is calculated to be a large number. It works because it is within vertical blank, but it reduces region of blank that can be used for power gating. [How] Calculation needs to convert micro seconds to number of vertical lines. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Reza Amini <reza.amini@amd.com> Tested-by:
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Leo Chen authored
[Why & How] DMUB may hang when powering down pixel clocks due to no dprefclk. It is fixed by exiting idle optimization before the attempt to access PHY. Reviewed-by:
Leo Chen <sancchen@amd.com> Tested-by:
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Wenjing Liu authored
[Why] Current recout calculation has a few assumptions and implementation for MPO + ODM combine calculation is very specific. The equation has too many cases without enough comments to document the detail. [How] The change remove the following assumptions: 1. When MPO is enabled, we only allow ODM Combine 2:1 2. ODM Combine always has even segment width. 3. Secondary MPO plane's pipe_ctx copies pre_odm_pipe from its top pipe. The change applies a generic formula with more details in comment to document this solution so it is eaiser to learn and debug later. Reviewed-by:
Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Acked-by:
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Martin Tsai authored
[Why] Panels show corruption with high refresh rate timings when ss is enabled. [How] Read down-spread percentage from lut to adjust dprefclk. Reviewed-by:
Martin Tsai <martin.tsai@amd.com> Tested-by:
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Alvin Lee authored
[Description] It is not valid to set the WDIVIDER value to 0, so do not re-write to DISPCLK_WDIVIDER if the current value is 0 (i.e., it is at it's initial value and we have not made any requests to change DISPCLK yet). Reviewed-by:
Saaem Rizvi <syedsaaem.rizvi@amd.com> Acked-by:
Alvin Lee <alvin.lee2@amd.com> Tested-by:
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Ethan Bitnun authored
[Description] - Prevent ODM pipe connections between pipes that are not part of the same plane when adding a plane to context - Re-attach child pipes of ODM slice about to be disconnected to prevent any lost pipes with invalid tops/bottoms - We cannot split if head_pipe is not in ODM. Preventing this avoids creating an invalid context with an invalid pipe. Reviewed-by:
Ethan Bitnun <ethan.bitnun@amd.com> Tested-by:
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Lijo Lazar authored
Not all rings have scheduler associated. Only update scheduler data for rings with scheduler. It could result in out of bound access as total rings are more than those associated with particular IPs. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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sguttula authored
This patch will enable VCN FW workaround using DRM KEY INJECT WORKAROUND method, which is helping in fixing the secure playback. Signed-off-by:
sguttula <Suresh.Guttula@amd.com> Reviewed-by:
Leo Liu <leo.liiu@amd.com> Signed-off-by:
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Iswara Nagulendran authored
[How & Why] When determining default aux backlight level, read from DPCD address 0x734 for VESA SCR on OLED. Reviewed-by:
Felipe Clark <felipe.clark@amd.com> Acked-by:
Iswara Nagulendran <iswara.nagulendran@amd.com> Tested-by:
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Srinivasan Shanmugam authored
Changed from pr_err/info to dev_* variants so that we get better debug info when there are multiple GPUs in the system. Fixes: 09edeb4c ("drm/radeon: Prefer pr_err/_info over printk") Suggested-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Conform to Linux kernel coding style. Fixes the following & other checks in radeon_encoders.c & radeon_gart.c: WARNING: Missing a blank line after declarations WARNING: Block comments use * on subsequent lines WARNING: Prefer 'unsigned int' to bare use of 'unsigned' WARNING: braces {} are not necessary for single statement blocks Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Fixes the below checkpatch.pl warnings: WARNING: Block comments use * on subsequent lines WARNING: Block comments use a trailing */ on a separate line WARNING: suspect code indent for conditional statements (8, 12) WARNING: braces {} are not necessary for single statement blocks Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: -
Srinivasan Shanmugam authored
Fixes the following: - WARNING: externs should be avoided in .c files - ERROR: do not initialise globals to 0 - WARNING: Missing a blank line after declarations Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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George Shen authored
[Why] Current yellow carp B0 PHYD32CLK logic is incorrectly applied to other ASICs. [How] Add guard to check chip family is yellow carp before applying logic. Reviewed-by:
Hansen Dsouza <hansen.dsouza@amd.com> Acked-by:
George Shen <george.shen@amd.com> Tested-by:
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Reza Amini authored
[Why] There are grammer mistakes in comments [How] Correct grammar mistakes Reviewed-by:
Anthony Koo <anthony.koo@amd.com> Acked-by:
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Srinivasan Shanmugam authored
Return -ENOMEM, when there is no sufficient dynamically allocated memory to create MQD backup for ring Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Fixes the following to align to coding style: WARNING: do not add new typedefs +typedef struct FW_ATT_DB_HEADER WARNING: do not add new typedefs +typedef struct FW_ATT_RECORD WARNING: Symbolic permissions 'S_IRUSR' are not preferred. Consider using octal permissions '0400'. + S_IRUSR, ERROR: "(foo*)" should be "(foo *)" WARNING: please, no space before tabs Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Adhere to linux coding style Fixes the following: WARNING: Prefer IS_ENABLED(<FOO>) to CONFIG_<FOO> || CONFIG_<FOO>_MODULE +#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) WARNING: Prefer IS_ENABLED(<FOO>) to CONFIG_<FOO> || CONFIG_<FOO>_MODULE +#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Jonathan Kim authored
MES can concurrently schedule queues on the device that require exclusive device access if marked exclusively_scheduled without the requirement of GWS. Similar to the F32 HWS, MES will manage quality of service for these queues. Use this for cooperative groups since cooperative groups are device occupancy limited. Since some GFX11 devices can only be debugged with partial CUs, do not allow the debugging of cooperative groups on these devices as the CU occupancy limit will change on attach. In addition, zero initialize the MES add queue submission vector for MES initialization tests as we do not want these to be cooperative dispatches. Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
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Horace Chen authored
[Why] Current SR-IOV will not set GC to off state, while it is a real GC hard reset. Whthout GFX off flag, driver may do gfxhub invalidation before firmware load and gfxhub gart enable. This operation may cause CP to become busy because GC is not in the right state for invalidation. [How] Add a function for SR-IOV to clean up some sw state before recover. Set adev->gfx.is_poweron to false to prevent gfxhub invalidation before gfx firmware autoload complete. Signed-off-by:
Horace Chen <horace.chen@amd.com> Reviewed-by:
HaiJun Chang <HaiJun.Chang@amd.com> Signed-off-by:
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Jane Jian authored
Report current GFX clock also from average clock value as the original CurrClock data is not valid/accurate any more as per FW team Signed-off-by:
Jane Jian <Jane.Jian@amd.com> Reviewed-by:
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- 21 Jul, 2023 10 commits
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Yang Li authored
Use colon to separate parameter name from their specific meaning. silence the warning: drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c:793: warning: Function parameter or member 'adev' not described in 'amdgpu_vm_pte_update_noretry_flags' Reviewed-by:
Randy Dunlap <rdunlap@infradead.org> Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Mario Limonciello authored
If the second call to amdgpu_bo_create_kernel() fails, the memory allocated from the first call should be cleared. If the third call fails, the memory from the second call should be cleared. Fixes: b95b5391 ("drm/amdgpu/psp: move PSP memory alloc from hw_init to sw_init") Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
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Victor Lu authored
An instance of for_each_inst() was not changed to match its new behaviour and is causing a loop. v2: remove tmp_mask variable Fixes: b579ea63 ("drm/amdgpu: Modify for_each_inst macro") Signed-off-by:
Victor Lu <victorchengchi.lu@amd.com> Acked-by:
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Lijo Lazar authored
XCP_CTL register is expected to be programmed by firmware. Under certain conditions FW may not have programmed it correctly. As a workaround, program it when FW has not programmed the right values. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Jonathan Kim authored
Update the list of devices that require the cwsr trap handling workaround for debugging use cases. Signed-off-by:
Ruili Ji <ruili.ji@amd.com> Reviewed-by:
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Samuel Holland authored
clang on RISC-V appears to be unaffected by the bug causing excessive stack usage in calculate_bandwidth(). clang 16 with -fstack-usage reports a 304 byte stack frame size with CONFIG_ARCH_RV32I, and 512 bytes with CONFIG_ARCH_RV64I. Reviewed-by:
Nathan Chancellor <nathan@kernel.org> Tested-by:
Samuel Holland <samuel.holland@sifive.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] Internal subvp state is not referenced in driver code, so it can be removed. Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Fixes the following checkpatch.pl: WARNING: printk() should include KERN_<LEVEL> facility level Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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sguttula authored
This patch will enable secure decode playback on VCN4_0_2 Signed-off-by:
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Mario Limonciello authored
The VBIOS part number is read both in amdgpu_atom_parse() as well as in atom_get_vbios_pn() and stored twice in the `struct atom_context` structure. Remove the first unnecessary read and move the `pr_info` line from that read into the second. v2: squash in unused variable removal Signed-off-by:
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- 18 Jul, 2023 7 commits
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Guchun Chen authored
~0 as no xcp partition is used in several places, so improve its definition by a macro for code consistency. Suggested-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Guchun Chen authored
Other PDs/PTs allocation should just use the same xcp_id as that stored in root PD. Suggested-by:
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Guchun Chen authored
Recent code set xcp_id stored from file private data when opening device to amdgpu bo for accounting memory usage etc, but not all VMs are attached to this fpriv structure like the vm cases in amdgpu_mes_self_test, otherwise, KASAN will complain below out of bound access. And more importantly, VM code should not touch fpriv structure, so drop fpriv code handling from amdgpu_vm_pt. [ 77.292314] BUG: KASAN: slab-out-of-bounds in amdgpu_vm_pt_create+0x17e/0x4b0 [amdgpu] [ 77.293845] Read of size 4 at addr ffff888102c48a48 by task modprobe/1069 [ 77.294146] Call Trace: [ 77.294178] <TASK> [ 77.294208] dump_stack_lvl+0x49/0x63 [ 77.294260] print_report+0x16f/0x4a6 [ 77.294307] ? amdgpu_vm_pt_create+0x17e/0x4b0 [amdgpu] [ 77.295979] ? kasan_complete_mode_report_info+0x3c/0x200 [ 77.296057] ? amdgpu_vm_pt_create+0x17e/0x4b0 [amdgpu] [ 77.297556] kasan_report+0xb4/0x130 [ 77.297609] ? amdgpu_vm_pt_create+0x17e/0x4b0 [amdgpu] [ 77.299202] __asan_load4+0x6f/0x90 [ 77.299272] amdgpu_vm_pt_create+0x17e/0x4b0 [amdgpu] [ 77.300796] ? amdgpu_init+0x6e/0x1000 [amdgpu] [ 77.302222] ? amdgpu_vm_pt_clear+0x750/0x750 [amdgpu] [ 77.303721] ? preempt_count_sub+0x18/0xc0 [ 77.303786] amdgpu_vm_init+0x39e/0x870 [amdgpu] [ 77.305186] ? amdgpu_vm_wait_idle+0x90/0x90 [amdgpu] [ 77.306683] ? kasan_set_track+0x25/0x30 [ 77.306737] ? kasan_save_alloc_info+0x1b/0x30 [ 77.306795] ? __kasan_kmalloc+0x87/0xa0 [ 77.306852] amdgpu_mes_self_test+0x169/0x620 [amdgpu] v2: without specifying xcp partition for PD/PT bo, the xcp id is -1. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2686 Fixes: 3ebfd221 ("drm/amdkfd: Store xcp partition id to amdgpu bo") Signed-off-by:
Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com> Reviewed-by:
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Guchun Chen authored
file_priv needs to be setup firstly, otherwise, root PD will always be allocated on partition 0, even if opening the device from other partitions. Fixes: 3ebfd221 ("drm/amdkfd: Store xcp partition id to amdgpu bo") Signed-off-by:
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Victor Lu authored
Add RLCG interface support for gfx v9.4.3 and multiple XCCs. Do not enable it yet. v2: Fix amdgpu_rlcg_reg_access_ctrl init, add support for multiple XCCs in amdgpu_mm_wreg_mmio_rlc v3: Use GET_INST() when indexing amdgpu_rlcg_reg_access_ctrl Signed-off-by:Zhigang Luo <zhigang.luo@amd.com> Signed-off-by:
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Aric Cyr authored
This version brings along following fixes: - Update 128b/132b downspread factor to 0.3% - Add helpers to get DMUB FW boot options - Initialize necessary uninitialized variables - Add stream overhead in BW calculations for 128b/132b - Add link encoding to timing BW calculation parameters - Prevent vtotal from being set to 0 - Fix race condition when turning off an output alone - Keep PHY active for DP displays on DCN31 - Fix ASIC check in aux timeout workaround - ABM pause toggle - Add missing triggers for full updates - Disable MPC split by default on special asic - Add additional refresh rate conditions for SubVP cases - Fix DP2 link training failure with RCO - Reenable all root clock gating options - Cache backlight_millinits in link structure and setting brightness accordingly - Refine to decide the verified link setting - Update SW cursor fallback for subvp high refresh Acked-by:
Alan Liu <haoping.liu@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
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Alvin Lee authored
[Description] - Full update was missed for the following cases: - Idle optimization is enabled - Plane is not in current context - Also don't clear surface updates at end of commit_plane_for_stream_fast as they are cleared at the beginning of each flip (only stream updates need to be cleared in case there is no stream update in the next flip) Reviewed-by:
Samson Tam <samson.tam@amd.com> Acked-by:
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