- 11 Sep, 2023 40 commits
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Yifan Zhang authored
gc info usage misses type conversion. Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
Li Ma <li.ma@amd.com> Signed-off-by:
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Qingqing Zhuo authored
[Why & How] Some registers are never used in the driver but defined. Remove them. Reviewed-by:
Roman Li <roman.li@amd.com> Acked-by:
Stylon Wang <stylon.wang@amd.com> Signed-off-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Dillon Varone authored
[WHY&HOW] Add support for programming dp dto via dccg. Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Dillon Varone <dillon.varone@amd.com> Tested-by:
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Wenjing Liu authored
[why] Current dc update design has limitation to support transition from ODM combine to minimum transition to MPC combine state seamlessly at the capability boundary when MPO plane is resizing. This will require dc update high level refactor in order to remove the design limitation. The decision is to block such use case for existing products by limiting ODM power optimization support for only those surfaces within guaranteed viewport size. This will prevent us from transitioning to MPC combine state when ODM power optimization is enabled. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Wenjing Liu authored
[why] In some cases such as 8k desktop surface with 144Hz timing, we decide to enable ODM power optimization but this surface doesn't have a minimum transition state. Therefore we cannot switch off ODM power optimization seamlessly This creates path depedency on ODM power optimization decision. i.e whether or not we should switch off ODM power optimization is dependent on if the transition to switch off ODM power optimization from current state is seamless. We don't desire a path dependent power optimization policy as it is too dynamic and difficult to maintain. [how] Attempt ODM power optimization only after we can validate new state without using pipe combine. Reviewed-by:
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Wenjing Liu authored
[why] The result of predict_pipe_split calculation is no longer used but the function is not removed. This will cause unnecessary calculation of pipe split prediction in every frame update. Reviewed-by:
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David Francis authored
The code in kfd_mqd_manager_v11.c to support criu dump and restore of queue state was missing. Added it; should be equivalent to kfd_mqd_manager_v10.c. CC: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Acked-by:
David Francis <David.Francis@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] For enabling automated testing, add a hook to DCHUBBUB interface so that mall status can be queried by userspace through debugfs. This removes dependence on requiring a userspace tool like UMR for querying status for MALL static screen IGT test. Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Ethan Bitnun authored
[Description] - Add new logs to be used by the AutoDPMTest - Enclose AutoDPMTest logs in settings - Add logging definition Reviewed-by:
Ethan Bitnun <etbitnun@amd.com> Tested-by:
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Paul Hsieh authored
[Why] Some panels request main link off before specific vertical line. If source turn off main link after specific vertical line then panel defect will be exposed. [How] Add interface to support turn off main link before specific vertical line Reviewed-by:
Robin Chen <robin.chen@amd.com> Acked-by:
Paul Hsieh <paul.hsieh@amd.com> Tested-by:
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Wayne Lin authored
[Why] In drm_dp_mst_topology_mgr_resume() today, it will resume the mst branch to be ready handling mst mode and also consecutively do the mst topology probing. Which will cause the dirver have chance to fire hotplug event before restoring the old state. Then Userspace will react to the hotplug event based on a wrong state. [How] Adjust the mst resume flow as: 1. set dpcd to resume mst branch status 2. restore source old state 3. Do mst resume topology probing For drm_dp_mst_topology_mgr_resume(), it's better to adjust it to pull out topology probing work into a 2nd part procedure of the mst resume. Will have a follow up patch in drm. Reviewed-by:
Wayne Lin <wayne.lin@amd.com> Tested-by:
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Mustapha Ghaddar authored
[HOW & Why] There seems to be an issue with 2nd DPIA acquiring link encoder for tiled displays. Solution is to remove check for eng_id before we get first dynamic encoder for it Reviewed-by:
Cruise Hung <cruise.hung@amd.com> Reviewed-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Acked-by:
Mustapha Ghaddar <mghaddar@amd.com> Tested-by:
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Mukul Joshi authored
Rename KGD_MAX_QUEUES to AMDGPU_MAX_QUEUES to conform with the naming convention followed in amdgpu_gfx.h. No functional change. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] build scaling param is overriding validation policy regarding small viewport support. Even if ODM + windowed MPO is not supported. The decision has to be made at the time of validation. When building scaling params, we might be building an initial dc state as an input to DML validation. The initial state is not supposed to be always valid and we rely on DML to modify the initial dc state and determine the final validation result. This check is pre judging validation result when building the initial dc state. This causes an issue where we are transitioning from desktop only ODM combine 2:1 to ODM bypass with 2 planes. In this case we are building an initial state with with ODM 2:1 combine + 2 planes. This is indeed not supported but DML is about to modify the state so it no longer uses ODM combine. Before it reaches DML, dc resource already fails validation because it checks that the initial state is not supported by our policy. This overrides the ODM decision to validate this state with ODM combine disabled. Therefore causes an unexpected validation failure when the secondary plane is added on one side of the screen. Reviewed-by:
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Nicholas Susanto authored
[Why] DML calculations differ with DCN3.1 spreadsheet values due to translations errors from the visual basic code [How] Add missing calculations that set the value for DSCDelay Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Nicholas Susanto <nicholas.susanto@amd.com> Tested-by:
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Tao Zhou authored
Print out row, column and bank value of UMC error address for UMC v12. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Hawking Zhang authored
So driver doesn't generate incorrect message until the new format is settled down for aqua_vanjaram Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Signed-off-by:
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Alex Deucher authored
Needed for HDP flush to work correctly. Reviewed-by:
Timmy Tsai <timmtsai@amd.com> Signed-off-by:
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Alex Deucher authored
This matches the behavior for soc15 and nv. Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Anthony Koo authored
- Add new params to dmub_feature_caps for checking replay support in FW Acked-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
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Swapnil Patel authored
[Why] Currently the driver looks DCN registers to access if BL is on or not. This check is not valid if we are using AUX based brightness control. This causes driver to not send out "backlight off" command during power off sequence as it already thinks it is off. [How] Only check DCN registers if we aren't using AUX based brightness control. Reviewed-by:
Swapnil Patel <swapnil.patel@amd.com> Tested-by:
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Dan Carpenter authored
This loop will exit with "retry" set to -1 if it fails but the code checks for if "retry" is zero. Fix this by changing post-op to a pre-op. --retry vs retry--. Fixes: e01eeffc ("drm/amd/pm: avoid driver getting empty metrics table for the first time") Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by:
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Bhawanpreet Lakha authored
Dirty rect can be used with replay, so enable them to allow for more powersaving. Reviewed-by:
Sun peng Li <sunpeng.li@amd.com> Acked-by:
Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Tested-by:
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Aurabindo Pillai authored
[Why&How] Set a default return value of -ENOTSUPP to indicate that the hardware does not support querying ODM Combine mode. Reviewed-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Acked-by:
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Hamza Mahfooz authored
This reverts commit 70e64c4d. Since, we now have an actual fix for this issue, we can get rid of this workaround as it can cause pin failures if enough VRAM isn't carved out by the BIOS. Cc: stable@vger.kernel.org # 6.1+ Acked-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Yifan Zhang authored
Dropping bit 31:4 of page table base is wrong, it makes page table base points to wrong address if phys addr is beyond 64GB; dropping page_table_start/end bit 31:4 is unnecessary since dcn20_vmid_setup will do that. Also, while we are at it, cleanup the assignments using upper_32_bits()/lower_32_bits() and AMDGPU_GPU_PAGE_SHIFT. Cc: stable@vger.kernel.org Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2354 Fixes: 81d0bcf9 ("drm/amdgpu: make display pinning more flexible (v2)") Acked-by:
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Alvin Lee authored
[Description] - When disabling a phantom pipe, we first enable the phantom OTG so the double buffer update can successfully take place - However, want to avoid locking the phantom otherwise setting DPG_EN=1 for the phantom pipe is blocked (without this we could hit underflow due to phantom HUBP being blanked by default) Reviewed-by:
Samson Tam <samson.tam@amd.com> Acked-by:
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Alvin Lee authored
[Description] Before enabling the phantom OTG for an update we must enable DPG to avoid underflow. Reviewed-by:
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Mukul Joshi authored
The CU mask passed from user-space will change based on different spatial partitioning mode. As a result, update CU masking code for GFX9.4.3 to work for all partitioning modes. Signed-off-by:
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Mukul Joshi authored
Update cache info reporting in sysfs to report the correct number of CUs and associated cache information based on different spatial partitioning modes. Signed-off-by:
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Tao Zhou authored
Get UMC phyical channel index according to node id, umc instance and channel instance. Signed-off-by:
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Yang Wang authored
v1: enable smu_v13_0_6 mca debug mode when UMC RAS feature is enabled. v2: use amdgpu_ras_is_supported() helper function instead bitmask check. Signed-off-by:
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Yang Wang authored
update smu firmware header to support smu mca debug feature. Signed-off-by:
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Tao Zhou authored
Convert MCA error address to physical address and find out all pages in one physical row. Signed-off-by:
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Lijo Lazar authored
When reset method is not passed in reset context, look for the handler for default reset method. On Aldebaran, default reset method for SOCs connected to CPU over XGMI is MODE2. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Asad Kamal <asad.kamal@amd.com> Tested-by:
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Mukul Joshi authored
Currently, we store CU info only for a single XCC assuming that it is the same for all XCCs. However, that may not be true. As a result, store CU info for all XCCs. This info is later used for CU masking. Signed-off-by:
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Ma Jun authored
[1] Remove the irq flags setting code since pci_alloc_irq_vectors() handles these flags. [2] Free the msi vectors in case of error. Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Acked-by:
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Lang Yu authored
Fixes: 5d5eac7e ("drm/amdgpu: add selftest framework for UMSCH") Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Reviewed-by:
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Mukul Joshi authored
This patch fixes the following unaligned 64-bit doorbell warning seen when submitting packets on HIQ on GFX v9.4.3 by making the HIQ doorbell 64-bit aligned. The warning is seen when GPU is loaded in any mode other than SPX mode. [ +0.000301] ------------[ cut here ]------------ [ +0.000003] Unaligned 64-bit doorbell [ +0.000030] WARNING: /amdkfd/kfd_doorbell.c:339 write_kernel_doorbell64+0x72/0x80 [ +0.000003] RIP: 0010:write_kernel_doorbell64+0x72/0x80 [ +0.000004] RSP: 0018:ffffc90004287730 EFLAGS: 00010246 [ +0.000005] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000000 [ +0.000003] RDX: 0000000000000001 RSI: ffffffff82837c71 RDI: 00000000ffffffff [ +0.000003] RBP: ffffc90004287748 R08: 0000000000000003 R09: 0000000000000001 [ +0.000002] R10: 000000000000001a R11: ffff88a034008198 R12: ffffc900013bd004 [ +0.000003] R13: 0000000000000008 R14: ffffc900042877b0 R15: 000000000000007f [ +0.000003] FS: 00007fa8c7b62000(0000) GS:ffff889f88400000(0000) knlGS:0000000000000000 [ +0.000004] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ +0.000003] CR2: 000056111c45aaf0 CR3: 00000001414f2002 CR4: 0000000000770ee0 [ +0.000003] PKRU: 55555554 [ +0.000002] Call Trace: [ +0.000004] <TASK> [ +0.000006] kq_submit_packet+0x45/0x50 [amdgpu] [ +0.000524] pm_send_set_resources+0x7f/0xc0 [amdgpu] [ +0.000500] set_sched_resources+0xe4/0x160 [amdgpu] [ +0.000503] start_cpsch+0x1c5/0x2a0 [amdgpu] [ +0.000497] kgd2kfd_device_init.cold+0x816/0xb42 [amdgpu] [ +0.000743] amdgpu_amdkfd_device_init+0x15f/0x1f0 [amdgpu] [ +0.000602] amdgpu_device_init.cold+0x1813/0x2176 [amdgpu] [ +0.000684] ? pci_bus_read_config_word+0x4a/0x80 [ +0.000012] ? do_pci_enable_device+0xdc/0x110 [ +0.000008] amdgpu_driver_load_kms+0x1a/0x110 [amdgpu] [ +0.000545] amdgpu_pci_probe+0x197/0x400 [amdgpu] Fixes: c3186665 ("drm/amdgpu: use doorbell mgr for kfd kernel doorbells") Signed-off-by:
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Mukul Joshi authored
This patch fixes the case where the code currently passes absolute register address and not the reg offset, which HWS expects, when sending the PM4 packet to set/update CWSR grace period. Additionally, cleanup the signature of build_grace_period_packet_info function as it no longer needs the inst parameter. Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Signed-off-by:
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