- 13 May, 2016 40 commits
-
-
Markos Chandras authored
This is similar to commit 934c7923 ("MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions"). The CACHE instruction has been redefined for MIPSr6 and it reduced its offset field to 8 bits. This leads to micro-assembler field overflow warnings when booting SMP MIPSr6 cores like the following one: Call Trace: [<ffffffff8010af88>] show_stack+0x68/0x88 [<ffffffff8056ddf0>] dump_stack+0x68/0x88 [<ffffffff801305bc>] warn_slowpath_common+0x8c/0xc8 [<ffffffff80130630>] warn_slowpath_fmt+0x38/0x48 [<ffffffff80125814>] build_insn+0x514/0x5c0 [<ffffffff806ee134>] cps_gen_cache_routine.isra.3+0xe0/0x1b8 [<ffffffff806ee570>] cps_pm_init+0x364/0x9ec [<ffffffff80100538>] do_one_initcall+0x90/0x1a8 [<ffffffff806e8c14>] kernel_init_freeable+0x160/0x21c [<ffffffff8056b6a0>] kernel_init+0x10/0xf8 [<ffffffff801059f8>] ret_from_kernel_thread+0x14/0x1c We fix this by incrementing the base register on every loop. Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com> Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12329/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
-
Markos Chandras authored
We shouldn't trust that the secondary cores will have a sane ebase register (either from the bootloader or during the hardware design phase) so use the ebase address as calculated by the boot CPU. Signed-off-by:
-
Paul Burton authored
MIPSr6 introduces support for "Virtual Processors", which are conceptually similar to VPEs from the now-deprecated MT ASE. Detect whether the system supports VPs using the VP bit in Config5, adding cpu_has_vp for use by later patches. Signed-off-by:
-
Antony Pavlov authored
The following features are supported: * UART; * SPI-flash; * USB host; * GPIO key and LED. Links: * https://dptechnics.com/shop/index.php?route=product/product&path=59&product_id=50 * https://dptechnics.com/shop/index.php?route=product/product&path=59&product_id=63Signed-off-by:
Antony Pavlov <antonynpavlov@gmail.com> Cc: Daan Pape <daan@dptechnics.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12886/Signed-off-by:
-
Antony Pavlov authored
Please see https://www.dptechnics.com/contact for details. Signed-off-by:
Rob Herring <robh@kernel.org> Cc: Daan Pape <daan@dptechnics.com> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12885/Signed-off-by:
-
Antony Pavlov authored
The following features are supported: * UART; * SPI-flash; * USB host; * GPIO key and LED. Please see https://onion.io/omega for details. Signed-off-by:
-
Antony Pavlov authored
Please see https://onion.io/contact for details. Signed-off-by:
-
Antony Pavlov authored
The following features are supported: * UART; * SPI-flash; * USB host; * GPIO keys and LEDs. Links: * http://www.dragino.com/products/mother-board/item/71-ms14-p.html * https://wiki.openwrt.org/toh/dragino/ms14Signed-off-by: -
Antony Pavlov authored
Please see http://www.dragino.com/about/about.html for details. Signed-off-by:
-
Antony Pavlov authored
The following features are supported: * UART; * SPI-flash; * USB host; * GPIO keys and LEDs. Links: * http://www.tp-link.com/en/products/details/?model=TL-MR3020 * http://wiki.openwrt.org/toh/tp-link/tl-mr3020 * https://wikidevi.com/wiki/TP-LINK_TL-MR3020Signed-off-by:
-
Antony Pavlov authored
Signed-off-by:
-
Antony Pavlov authored
This patch introduces devicetree for Atheros AR9331 SoC (AKA Hornet). The AR9331 chip is a Wi-Fi System-On-Chip (WiSOC), typically used in very cheap Access Points and Routers. Signed-off-by:
-
Antony Pavlov authored
For OF boards we have to skip platform initialization code so we can prove that OF code do all necessary initialization. [ralf@linux-mips.org: Fix merge conflict.] Signed-off-by:
Sudip Mukherjee <sudip.mukherjee@codethink.co.uk> Reviewed-by:
Marek Vasut <marex@denx.de> Cc: Alban Bedel <albeu@free.fr> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12877/ Patchwork: https://patchwork.linux-mips.org/patch/12920/Signed-off-by:
-
Antony Pavlov authored
Current ath79 clock.c code does not read reference clock and pll setup from devicetree. E.g. you can set any clock rate value in board DTS but it will have no effect on the real clk calculation. This patch fixes some AR9132 devicetree clock support defects: * clk initialization function ath79_clocks_init_dt_ng() is introduced; it actually gets pll block base register address and reference clock from devicetree; * pll register parsing code is moved to the separate ar724x_clk_init() function; this function can be called from platform code or from devicetree code. Also mips_hpt_frequency value is set from dt, so the appropriate clock parameter is added to the cpu@0 devicetree node. The same approach can be used for adding AR9331 devicetree support. Signed-off-by: -
Antony Pavlov authored
The include/dt-bindings/clock/ath79-clk.h header file is introduced so we can use symbolic identifiers for SoC clocks. Signed-off-by:
-
Antony Pavlov authored
Here are some Sascha Hauer's arguments for using aliases in the dts files: - using aliases reduces the number of indentations in dts files; - dts files become independent of the layout of the dtsi files (it becomes possible to introduce another bus {} hierarchy between a toplevel bus and the devices when you have to); - less chances for typos. if &i2c2 does not exist you get an error. If instead you duplicate the whole path in the dts file a typo in the path will just create another node. Signed-off-by: -
Antony Pavlov authored
The TP-LINK TL-WR1043ND board has only one serial port, so replacing the default of 0 with 0 does nothing useful. Moreover, the correct name for aliases node is "aliases" not "alias". An overview of the "aliases" node usage can be found on the device tree usage page at devicetree.org [1]. Also please see chapter 3.3 ("Aliases node") of the ePAPR 1.1 [2]. [1] http://devicetree.org/Device_Tree_Usage#aliases_Node [2] https://www.power.org/documentation/epapr-version-1-1/Signed-off-by:Alban Bedel <albeu@free.fr> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12872/Signed-off-by:
-
Hauke Mehrtens authored
Now it is possible to build in no device tree at all and depend on the boot loader providing one or someone concatenating a device tree to the end of the image. This was copied from arch/mips/bmips/Kconfig Signed-off-by:
Hauke Mehrtens <hauke@hauke-m.de> Acked-by:
John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12899/Signed-off-by:
-
Hauke Mehrtens authored
This fetches the device tree file like it is specified in the MIPS UHI interface if one was found. This is also used when the device tree file was appended to the kernel image with cat. This code is copied from arch/mips/bmips/setup.c. Signed-off-by:
-
Aaro Koskinen authored
Add DTS for EdgeRouter Lite that is usable as is without any "pruning" with APPENDED_DTB. Compared to builtin generic DTB, we can avoid errors and delays from probing non-existent I2C devices. Signed-off-by:
Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by:
-
Aaro Koskinen authored
Add DTS for D-Link DSR-1000N that is usable as is without any "pruning" with APPENDED_DTB. Split out the common parts from octeon_3xxx.dts into octeon_3xxx.dtsi. Compared to builtin generic DTB, we can specificy fixed links properly and avoid probing non-existent I2C devices. Signed-off-by:
-
Aaro Koskinen authored
MIPS wants to sleep 5 seconds before panicking when panic_on_oops is set, with no apparent reason. Remove this feature, since some users may want their systems to fail as quickly as possible. Users who want to delay reboot after panic can use PANIC_TIMEOUT. Signed-off-by:
-
Rafał Miłecki authored
Broadcom ARM home routers store SPROM content in NVRAM just like MIPS ones. To share SPROM code we need to move it out of arch/mips/ to some common place. We already have bcm47xx_nvram in firmware path and SPROM should fit there as well. This driver is responsible for parsing SoC configuration data into a struct shared between ssb and bcma buses. This was tested with BCM4706 & BCM5357C0 (BCM47XX) and BCM4708A0 (ARCH_BCM_5301X). Signed-off-by:
Rafał Miłecki <zajec5@gmail.com> Cc: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12210/Signed-off-by:
-
Philipp Zabel authored
The reset_ops structure is never modified. Make it const. Signed-off-by:
Philipp Zabel <p.zabel@pengutronix.de> Acked-by:
-
Philipp Zabel authored
The reset_ops structure is never modified. Make it const. Signed-off-by:
-
Aaro Koskinen authored
Fill MAC addresses from bootinfo when using appended DTB. Signed-off-by:
David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12590/Signed-off-by:
-
Aaro Koskinen authored
Don't fill MAC address if it's already set. This allows DTB to override the bootinfo. Signed-off-by:
-
Aaro Koskinen authored
Use separate pass to fill MAC addresses. This is needed because we want to do this also for the appended DTB. Signed-off-by:
-
Aaro Koskinen authored
Use model string from DTB for board type if the board is unknown. This is more informative, e.g. with EdgeRouter Pro the /proc/cpuinfo will display "ubnt,e200 (CN6120p1.1-1000-NSP)" instead of misleading "Unsupported Board". Signed-off-by:
-
Aaro Koskinen authored
Initialize system type string after device tree init. Signed-off-by:
-
Aaro Koskinen authored
Return NULL for unsupported board. Signed-off-by:
-
David Daney authored
Use the trigger type passed in to the function instead of reading it back out of the irq_data. Signed-off-by:
-
David Daney authored
OCTEON chips with the CIU3 interrupt controller use a different IPI mechanism that previous models. Add plat_smp_ops for the cn78xx and probing code to choose between the two types of ops. Signed-off-by:
-
David Daney authored
Add irq_chip support for both IPI and "normal" interrupts of the CIU3 controller. Document the device tree binding for the CIU3. Some functions are non-static as they will be used by follow-on support for MSI-X. Signed-off-by:
-
David Daney authored
Attempts to read the nonexistent registers results in bus errors. Either use registers that exist, or don't do the access as appropriate. Signed-off-by:
-
David Daney authored
Follow on patchs need to be able to distinguish the new models. Signed-off-by:
-
David Daney authored
These new members of the OCTEON III family have some new registers, update some of the definitions for use in follow on patches. Signed-off-by:
-
David Daney authored
Per the subject, always select HANDLE_DOMAIN_IRQ, and implement set_irq_regs() so that it actually works. Signed-off-by:
-
David Daney authored
Follow-on patches for OCTEON III will increase the number of irqs to potentially more than 256. Increase the width of the octeon_irq_ciu_to_irq to int to be able to handle this case. Remove the hacky code that verified that u8 would not be overflowed. Signed-off-by:
-
David Daney authored
To support more than 48 CPUs, the bootinfo structure grows a new coremask structure. Add the definition of the structure and add it to struct cvmx_bootinfo. In prom_init(), copy the new coremask data into the sysinfo structure, and use it in smp_setup(). Signed-off-by:
-
