- 21 Sep, 2023 3 commits
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Javier Pello authored
There is an assertion in ggtt_reserve_guc_top that the global GTT is of size at least GUC_GGTT_TOP, which is not the case on a 32-bit platform; see commit 562d55d9 ("drm/i915/bdw: Only use 2g GGTT for 32b platforms"). If GEM_BUG_ON is enabled, this triggers a BUG(); if GEM_BUG_ON is disabled, the subsequent reservation fails and the driver fails to initialise the device: i915 0000:00:02.0: [drm:i915_init_ggtt [i915]] Failed to reserve top of GGTT for GuC i915 0000:00:02.0: Device initialization failed (-28) i915 0000:00:02.0: Please file a bug on drm/i915; see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details. i915: probe of 0000:00:02.0 failed with error -28 Make the reservation at the top of the available space, whatever that is, instead of assuming that the top will be GUC_GGTT_TOP. Fixes: 91180076 ("drm/i915/uc: Reserve upper range of GGTT") Link: https://gitlab.freedesktop.org/drm/intel/-/issues/9080Signed-off-by:
Javier Pello <devel@otheo.eu> Reviewed-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Fernando Pacheco <fernando.pacheco@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: intel-gfx@lists.freedesktop.org Cc: stable@vger.kernel.org # v5.3+ Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230902171039.2229126186d697dbcf62d6d8@otheo.eu
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Badal Nilawar authored
It has been observed sometimes RC6 status register's unused bits are being set by h/w, without affecting RC6 functionality therefore updating the mask with used bits accordingly. As mtl_drpc is debugfs function, removing MISSING_CASE from default case as it doesn't make sense to panic (panic_on_warn=1) the CI system if register is reporting unsupported state. Cc: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by:
Badal Nilawar <badal.nilawar@intel.com> Reviewed-by:
Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by:
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Matthew Wilcox (Oracle) authored
The folio conversion changed the behaviour of shmem_sg_alloc_table() to put the entire length of the last folio into the sg list, even if the sg list should have been shorter. gen8_ggtt_insert_entries() relied on the list being the right length and would overrun the end of the page tables. Other functions may also have been affected. Clamp the length of the last entry in the sg list to be the expected length. Signed-off-by:
Matthew Wilcox (Oracle) <willy@infradead.org> Fixes: 0b62af28 ("i915: convert shmem_sg_free_table() to use a folio_batch") Cc: stable@vger.kernel.org # 6.5.x Link: https://gitlab.freedesktop.org/drm/intel/-/issues/9256 Link: https://lore.kernel.org/lkml/6287208.lOV4Wx5bFT@natalenko.name/Reported-by:
Oleksandr Natalenko <oleksandr@natalenko.name> Tested-by:
Andrzej Hajda <andrzej.hajda@intel.com> Signed-off-by:
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- 20 Sep, 2023 1 commit
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Justin Stitt authored
`strncpy` is deprecated for use on NUL-terminated destination strings [1]. We should prefer more robust and less ambiguous string interfaces. A suitable replacement is `strscpy` [2] due to the fact that it guarantees NUL-termination on the destination buffer without unnecessarily NUL-padding. `ctx` is zero allocated and as such strncpy's NUL-padding behavior was strictly a performance hit which is now resolved. Link: https://www.kernel.org/doc/html/latest/process/deprecated.html#strncpy-on-nul-terminated-strings [1] Link: https://manpages.debian.org/testing/linux-manual-4.8/strscpy.9.en.html [2] Link: https://github.com/KSPP/linux/issues/90 Cc: linux-hardening@vger.kernel.org Signed-off-by:
Justin Stitt <justinstitt@google.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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- 19 Sep, 2023 3 commits
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Alan Previn authored
On Meteorlake onwards, HW specs require that all user contexts that run on render or compute engines and require PXP must enforce run-alone bit in lrc. Add this enforcement for protected contexts. Signed-off-by:
Alan Previn <alan.previn.teres.alexis@intel.com> Reviewed-by:
Vivaik Balasubrawmanian <vivaik.balasubrawmanian@intel.com> Signed-off-by:
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Alan Previn authored
Update the GSC-fw input/output HECI packet size to match updated internal fw specs. Signed-off-by:
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Alan Previn authored
Update the max GSC-fw response time to match updated internal fw specs. Because this response time is an SLA on the firmware, not inclusive of i915->GuC->HW handoff latency, when submitting requests to the GSC fw via intel_gsc_uc_heci_cmd_submit helpers, start the count after the request hits the GSC command streamer. Also, move GSC_REPLY_LATENCY_MS definition from pxp header to intel_gsc_uc_heci_cmd_submit.h since its for any GSC HECI packet. Signed-off-by:
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- 15 Sep, 2023 3 commits
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Daniele Ceraolo Spurio authored
If we can't load the HuC due to an injected failure, we don't want to throw and error and trip CI. Using the gt_probe_error macro for logging ensure that the error is only printed if it wasn't explicitly injected. v2: keep the line to less than 100 characters (checkpatch). Link: https://gitlab.freedesktop.org/drm/intel/-/issues/7061Signed-off-by:
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Umesh Nerlige Ramappa authored
engine->stats is a union of execlist and guc stat objects. When execlist specific fields are initialized, the initial state of guc stats is affected. This results in bad busyness values when using GuC mode. Move the execlist initialization from common code to execlist specific code. Fixes: 77cdd054 ("drm/i915/pmu: Connect engine busyness stats from GuC to pmu") Signed-off-by:
Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Reviewed-by:
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Dnyaneshwar Bhadane authored
Invalidate instruction and State cache bit using INDIRECT_CTX on every gpu context switch for gen12. The goal of this workaround is to actually perform an explicit invalidation of that cache (by re-writing the register) during every GPU context switch, which is accomplished via a "workaround batchbuffer" that's attached to the context via INDIRECT_CTX. (Matt Roper) Please refer [1] for more reviews and comment on the same patch [1] https://patchwork.freedesktop.org/series/123377/ v2: - Remove extra parentheses from the condition (Lucas) - Align spacing and new line (Lucas) v3: - Fix commit message. v4: - Only Gen12 changes are kept and Remove DG2+ condition (Matt Roper) - Fix the commit message for r-b (Matt Roper) - Rename the register bit in define v5: - Move out this workaround from golden context init (Matt Roper) - Use INDIRECT_CTX to set bit on each GPU context switch (Matt Roper) v6: - Change IP Version base condition for Gen12 (Matt Roper) - Made imperative form of commit version messages (Suraj) - s/Added/Add in patch header (Suraj) v7: - In version descriptions s/Ropper/Roper (Matt Atwood) BSpec: 11354 Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by:
Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Reviewed-by:
Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
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- 14 Sep, 2023 1 commit
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Dan Carpenter authored
Move the check for "if (IS_ERR(obj))" in front of the call to i915_gem_object_set_cache_coherency() which dereferences "obj". Otherwise it will lead to a crash. Fixes: 43aa755e ("drm/i915/mtl: Update cache coherency setting for context structure") Signed-off-by:
Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by:
Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by:
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- 13 Sep, 2023 1 commit
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Andrzej Hajda authored
Some DG2 firmware locks this register for modification. Using wa_add with read_mask 0 allows to skip checks of such registers. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8945Signed-off-by:
Nirmoy Das <nirmoy.das@intel.com> Reviewed-by:
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- 08 Sep, 2023 1 commit
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Tvrtko Ursulin authored
Walk all GTs when doing the respective bits of drop_caches work. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by:
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- 07 Sep, 2023 2 commits
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Matt Roper authored
Drop Wa_14017240301, which is only relevant to pre-production MTL hardware. Although we usually wait a little bit longer to start dropping pre-production workarounds for a platform, it was suggested to eliminate this one slightly earlier because it's a bit unusual/ugly: this workaround is a display-specific workaround that requires matching on the graphics/GT IP version instead of the display IP version. Suggested-by:
Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by:
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Shekhar Chauhan authored
Disables Atomic-chaining of Typed Writes. BSpec: 54040 Signed-off-by:
Shekhar Chauhan <shekhar.chauhan@intel.com> Reviewed-by:
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- 31 Aug, 2023 1 commit
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Jonathan Cavitt authored
The thread_global_copy subtest of the live migrate selftest creates a large number of threads and waits 10ms for them all to start. This is not enough time to wait for the threaded tasks to start, as some may need to wait for additional ring space to be granted. Threads that do so are at risk of getting stopped (signaled) in the middle of waiting for additional space, which can result in ERESTARTSYS getting reported erroneously by i915_request_wait. Instead of waiting a flat 10ms for the threads to start, wait 10ms per thread. This grants enough of a buffer for each thread to wait for additional ring space when needed. Signed-off-by:
Jonathan Cavitt <jonathan.cavitt@intel.com> Reviewed-by:
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- 30 Aug, 2023 1 commit
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Andrzej Hajda authored
References to i915_requests may be trapped by userspace inside a sync_file or dmabuf (dma-resv) and held indefinitely across different proceses. To counter-act the memory leaks, we try to not to keep references from the request past their completion. On the other side on fence release we need to know if rq->engine is valid and points to hw engine (true for non-virtual requests). To make it possible extra bit has been added to rq->execution_mask, for marking virtual engines. Fixes: bcb9aa45 ("Revert "drm/i915: Hold reference to intel_context over life of i915_request"") Signed-off-by:
Chris Wilson <chris.p.wilson@linux.intel.com> Signed-off-by:
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- 29 Aug, 2023 1 commit
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Tejas Upadhyay authored
Now this workaround is permanent workaround on MTL and DG2, earlier we used to apply on MTL A0 step only. VLK-45480 Fixes: d922b80b ("drm/i915/gt: Add workaround 14016712196") Signed-off-by:
Tejas Upadhyay <tejas.upadhyay@intel.com> Acked-by:
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- 28 Aug, 2023 1 commit
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Daniele Ceraolo Spurio authored
Add FW definition and the matching override modparam. The GSC FW has both a release version, based on platform and a rolling counter, and a compatibility version, which is the one tracking interface changes. Since what we care about is the interface, we use the compatibility version in the binary names. Same as with the GuC, a major version bump indicate a backward-incompatible change, while a minor version bump indicates a backward-compatible one, so we use only the former in the file name. Signed-off-by:
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- 23 Aug, 2023 1 commit
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Nemesa Garg authored
Arrowlake-S graphics is similar enough to Meteorlake that we can treat them as the same platform Signed-off-by:
Nemesa Garg <nemesa.garg@intel.com> Reviewed-by:
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- 22 Aug, 2023 1 commit
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John Harrison authored
If GuC hits an internal error (and survives long enough to report it to the KMD), it is basically toast and will stop until a GT reset and subsequent GuC reload is performed. Previously, the KMD just printed an error message and then waited for the heartbeat to eventually kick in and trigger a reset (assuming the heartbeat had not been disabled). Instead, force the reset immediately to guarantee that it happens and to eliminate the very long heartbeat delay. The captured error state is also more likely to be useful if captured at the time of the error rather than many seconds later. Note that it is not possible to trigger a reset from with the G2H handler itself. The reset prepare process involves flushing outstanding G2H contents. So a deadlock could result. Instead, the G2H handler queues a worker thread to do the reset asynchronously. v2: Flush the worker on suspend and shutdown. Add rate limiting to prevent spam from a totally dead system (review feedback from Daniele). Signed-off-by:
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- 21 Aug, 2023 7 commits
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Matt Roper authored
Many of the IS_METEORLAKE conditions throughout the driver are supposed to be checks for Xe_LPG and/or Xe_LPM+ IP, not for the MTL platform specifically. Update those checks to ensure that the code will still operate properly if/when these IP versions show up on future platforms. v2: - Update two more conditions (one for pg_enable, one for MTL HuC compatibility). v3: - Don't change GuC/HuC compatibility check, which sounds like it truly is specific to the MTL platform. (Gustavo) - Drop a non-lineage workaround number for the OA timestamp frequency workaround. (Gustavo) Cc: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by:
Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230821180619.650007-20-matthew.d.roper@intel.com
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Matt Roper authored
Now that we properly match the Xe_LPG IP versions associated with various workarounds, there's no longer any need to define separate MTL subplatform in the driver. Nothing in the code is conditional on MTL-M or MTL-P base platforms. Furthermore, I'm not sure the "M" and "P" designations are even an accurate representation of which specific platforms would have which IP versions; those were mostly just placeholders from a long time ago. The reality is that the IP version present on a platform gets read from a fuse register at driver init; we shouldn't be trying to guess which IP is present based on PCI ID anymore. Signed-off-by:
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Matt Roper authored
Stepping-specific media behavior shouldn't be tied to MTL as a platform, but rather specifically to the Xe_LPM+ IP. Future non-MTL platforms may re-use this IP and will need to follow the exact same logic and apply the same workarounds. IS_MTL_MEDIA_STEP() is dropped in favor of IS_MEDIA_GT_IP_STEP, which checks the media IP version associated with a specific IP and also ensures that we're operating on the media GT, not the primary GT. v2: - Switch to the IS_GT_IP_STEP macro. v3: - Switch back to long-form IS_MEDIA_GT_IP_STEP. (Jani) v4: - Build IS_MEDIA_GT_IP_STEP on top of IS_MEDIA_GT_IP_RANGE and IS_MEDIA_STEP building blocks and name the parameters from/until rather than begin/fixed.. (Jani) v5: - Tweak macro comment wording. (Gustavo) - Add a check to catch NULL gt in IS_MEDIA_GT_IP_RANGE; this allows it to be used safely on i915->media_gt, which may be NULL on some platforms. (Gustavo) Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by:
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Matt Roper authored
Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none of these workarounds are actually tied to MTL as a platform; they only relate to the Xe_LPG graphics IP, regardless of what platform it appears in. At the moment MTL is the only platform that uses Xe_LPG with IP versions 12.70 and 12.71, but we can't count on this being true in the future. Switch these to use a new IS_GFX_GT_IP_STEP() macro instead that is purely based on IP version. IS_GFX_GT_IP_STEP() is also GT-based rather than device-based, which will help prevent mistakes where we accidentally try to apply Xe_LPG graphics workarounds to the Xe_LPM+ media GT and vice-versa. v2: - Switch to a more generic and shorter IS_GT_IP_STEP macro that can be used for both graphics and media IP (and any other kind of GTs that show up in the future). v3: - Switch back to long-form IS_GFX_GT_IP_STEP macro. (Jani) - Move macro to intel_gt.h. (Andi) v4: - Build IS_GFX_GT_IP_STEP on top of IS_GFX_GT_IP_RANGE and IS_GRAPHICS_STEP building blocks and name the parameters from/until rather than begin/fixed. (Jani) - Fix usage examples in comment. v5: - Tweak comment on macro. (Gustavo) Cc: Gustavo Sousa <gustavo.sousa@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Andi Shyti <andi.shyti@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by:
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Matt Roper authored
Although some of our Xe_LPG workarounds were already being applied based on IP version correctly, others were matching on MTL as a base platform, which is incorrect. Although MTL is the only platform right now that uses Xe_LPG IP, this may not always be the case. If a future platform re-uses this graphics IP, the same workarounds should be applied, even if it isn't a "MTL" platform. We were also incorrectly applying Xe_LPG workarounds/tuning to the Xe_LPM+ media IP in one or two places; we should make sure that we don't try to apply graphics workarounds to the media GT and vice versa where they don't belong. A new helper macro IS_GT_IP_RANGE() is added to help ensure this is handled properly -- it checks that the GT matches the IP type being tested as well as the IP version falling in the proper range. Note that many of the stepping-based workarounds are still incorrectly checking for a MTL base platform; that will be remedied in a later patch. v2: - Rework macro into a slightly more generic IS_GT_IP_RANGE() that can be used for either GFX or MEDIA checks. v3: - Switch back to separate macros for gfx and media. (Jani) - Move macro to intel_gt.h. (Andi) Cc: Gustavo Sousa <gustavo.sousa@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by:
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Matt Roper authored
The currently implemented Xe_LPM+ workarounds are specific to media version 13.00. When new IP versions show up in the future, they'll need their own workaround lists. Signed-off-by:
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Matt Roper authored
The workaround bounds for Wa_22011802037 are somewhat complex and are replicated in several places throughout the code. Pull the condition out to a helper function to prevent mistakes if this condition needs to change again in the future. Signed-off-by:
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- 17 Aug, 2023 3 commits
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Matt Roper authored
Wa_16011777198 only applies to pre-production steppings of DG2, which we're no longer supporting. Remove the workaround and override_gucrc handling, which is no longer needed. Since this was the final use of IS_DG2_GRAPHICS_STEP, that macro can also be removed now. v2: - Include the promised removal of override_gucrc handling. Cc: Ashutosh Dixit <ashutosh.dixit@intel.com> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Signed-off-by:
Ashutosh Dixit <ashutosh.dixit@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230816214824.548575-2-matthew.d.roper@intel.com
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Matt Roper authored
Removal of the DG2 pre-production workarounds has left duplicate condition blocks in a couple places, as well as some inconsistent platform ordering. Reshuffle and consolidate some of the workarounds to reduce the number of condition blocks and to more consistently follow the "newest platform first" convention. Code movement only; no functional change. Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
Matt Atwood <matthew.s.atwood@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230816214201.534095-11-matthew.d.roper@intel.com
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Matt Roper authored
DG2 first production steppings were C0 (for DG2-G10), B1 (for DG2-G11), and A1 (for DG2-G12). Several workarounds that apply onto to pre-production hardware can be dropped. Furthermore, several workarounds that apply to all production steppings can have their conditions simplified to no longer check the GT stepping. v2: - Keep Wa_16011777198 in place for now; it will be removed separately in a follow-up patch to keep review easier. Bspec: 44477 Signed-off-by:
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- 16 Aug, 2023 1 commit
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Jonathan Cavitt authored
Align igt_spinner_create_request with the hang_create_request implementation in selftest_hangcheck.c. Signed-off-by:
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- 15 Aug, 2023 2 commits
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Shekhar Chauhan authored
Since this Wa is specific to DirectX, this is not required on Linux. Signed-off-by:
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Alan Previn authored
When getting the next gt's seqno to be stored into an objects mm.tlb[gt_id] array, fix the retrieval code to get it from the correct gt instead of the same one. Fixes: d6c531ab ("drm/i915: Invalidate the TLBs on each GT") Signed-off-by:
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- 10 Aug, 2023 4 commits
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John Harrison authored
It was noticed that if the very first 'stealing' request failed to create for some reason then the 'steal all ids' loop would immediately exit with 'last' still being NULL. The test would attempt to continue but using a null pointer. Fix that by aborting the test if it fails to create any requests at all. Signed-off-by:
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Jonathan Cavitt authored
WA_22016122933 was recently applied to all MeteorLake engines, which is simultaneously too broad (should only apply to Media engines) and too specific (should apply to all platforms that use the same media engine as MeteorLake). Correct this in cases where coherency settings are modified. There were also two additional places where the workaround was applied unconditionally. The change was confirmed as necessary for all platforms, so the workaround label was removed. Suggested-by:
Fei Yang <fei.yang@intel.com> Reviewed-by:
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Jonathan Cavitt authored
Refactor i915_coherent_map_type to be GT-centric rather than device-centric. Each GT may require different coherency handling due to hardware workarounds. Since the function now takes a GT instead of the i915, the function is renamed and moved to the gt folder. Suggested-by:
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Jonathan Cavitt authored
The object pin created for shmem_create_from_object is just a single use mapping with the sole purpose of reading the contents of the whole object in bulk. And the whole source object is also even a throw-away. Ergo, the additional logic required by i915_coherent_map_type can be safely dropped and simplified. Suggested-by:
Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by:
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- 07 Aug, 2023 2 commits
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Joonas Lahtinen authored
Need to pull in b3e4aae6 ("drm/i915/hdcp: Modify hdcp_gsc_message msg sending mechanism") as a dependency for https://patchwork.freedesktop.org/series/121735/Signed-off-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
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Dave Airlie authored
Merge tag 'drm-intel-gt-next-2023-08-04' of git://anongit.freedesktop.org/drm/drm-intel into drm-next Driver Changes: - Avoid infinite GPU waits by avoidin premature release of request's reusable memory (Chris, Janusz) - Expose RPS thresholds in sysfs (Tvrtko) - Apply GuC SLPC min frequency softlimit correctly (Vinay) - Restore SLPC efficient freq earlier (Vinay) - Consider OA buffer boundary when zeroing out reports (Umesh) - Extend Wa_14015795083 to TGL, RKL, DG1 and ADL (Matt R) - Fix context workarounds with non-masked regs on MTL/DG2 (Lucas) - Enable the CCS_FLUSH bit in the pipe control and in the CS for MTL+ (Andi) - Update MTL workarounds 14018778641, 22016122933 (Tejas, Zhanjun) - Ensure memory quiesced before AUX CCS invalidation (Jonathan) - Add a gsc_info debugfs (Daniele) - Invalidate the TLBs on each GT on multi-GT device (Chris) - Fix a VMA UAF for multi-gt platform (Nirmoy) - Do not use stolen on MTL due to HW bug (Nirmoy) - Check HuC and GuC version compatibility on MTL (Daniele) - Dump perf_limit_reasons for slow GuC init debug (Vinay) - Replace kmap() with kmap_local_page() (Sumitra, Ira) - Add sentinel to xehp_oa_b_counters for KASAN (Andrzej) - Add the gen12_needs_ccs_aux_inv helper (Andi) - Fixes and updates for GSC memory allocation (Daniele) - Fix one wrong caching mode enum usage (Tvrtko) - Fixes for GSC wakeref (Alan) - Static checker fixes (Harshit, Arnd, Dan, Cristophe, David, Andi) - Rename flags with bit_group_X according to the datasheet (Andi) - Use direct alias for i915 in requests (Andrzej) - Replace i915->gt0 with to_gt(i915) (Andi) - Use the i915_vma_flush_writes helper (Tvrtko) - Selftest improvements (Alan) - Remove dead code (Tvrtko) Signed-off-by:
Dave Airlie <airlied@redhat.com> # Conflicts: # drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ZMy6kDd9npweR4uy@jlahtine-mobl.ger.corp.intel.com
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