- 15 Mar, 2024 3 commits
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Palmer Dabbelt authored
Yu Chien Peter Lin <peterlin@andestech.com> says: This patch series introduces the Andes PMU extension, which serves the same purpose as Sscofpmf and Smcntrpmf. Its non-standard local interrupt is assigned to bit 18 in the custom S-mode local interrupt enable and pending registers (slie/slip), while the interrupt cause is (256 + 18). * b4-shazam-merge: riscv: andes: Support specifying symbolic firmware and hardware raw events riscv: dts: renesas: Add Andes PMU extension for r9a07g043f dt-bindings: riscv: Add Andes PMU extension description perf: RISC-V: Introduce Andes PMU to support perf event sampling perf: RISC-V: Eliminate redundant interrupt enable/disable operations riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC dt-bindings: riscv: Add Andes interrupt controller compatible string riscv: errata: Rename defines for Andes Link: https://lore.kernel.org/r/20240222083946.3977135-1-peterlin@andestech.comSigned-off-by:
Palmer Dabbelt <palmer@rivosinc.com>
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Palmer Dabbelt authored
I'm picking this up on top of the broken patch for the merge window, as the offending patch breaks the rv32 build and was itself a fix so isn't on for-next. * b4-shazam-merge: riscv: Fix compilation error with FAST_GUP and rv32 riscv: Fix pte_leaf_size() for NAPOT Revert "riscv: mm: support Svnapot in huge vmap" Link: https://lore.kernel.org/r/20240304080247.387710-1-alexghiti@rivosinc.comSigned-off-by:
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Alexandre Ghiti authored
By surrounding the definition of pte_leaf_size() with a ifdef napot as it should have been. Fixes: e0fe5ab4 ("riscv: Fix pte_leaf_size() for NAPOT") Signed-off-by:
Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by:
Randy Dunlap <rdunlap@infradead.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Link: https://lore.kernel.org/r/20240304080247.387710-1-alexghiti@rivosinc.comSigned-off-by:
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- 12 Mar, 2024 9 commits
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Locus Wei-Han Chen authored
Add the Andes AX45 JSON files that allows specifying symbolic event names for the raw PMU events. Signed-off-by:
Locus Wei-Han Chen <locus84@andestech.com> Reviewed-by:
Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by:
Charles Ci-Jyun Wu <dminus@andestech.com> Reviewed-by:
Leo Yu-Chi Liang <ycliang@andestech.com> Tested-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by:
Atish Patra <atishp@rivosinc.com> Acked-by:
Ian Rogers <irogers@google.com> Link: https://lore.kernel.org/r/20240222083946.3977135-11-peterlin@andestech.comSigned-off-by:
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Yu Chien Peter Lin authored
xandespmu stands for Andes Performance Monitor Unit extension. Based on the added Andes PMU ISA string, the SBI PMU driver will make use of the non-standard irq source. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
Conor Dooley <conor.dooley@microchip.com> Acked-by:
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Yu Chien Peter Lin authored
Document the ISA string for Andes Technology performance monitor extension which provides counter overflow interrupt and mode filtering mechanisms. Signed-off-by:
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Yu Chien Peter Lin authored
Assign riscv_pmu_irq_num the value of (256 + 18) for the custome PMU and add SSCOUNTOVF and SIP alternatives to ALT_SBI_PMU_OVERFLOW() and ALT_SBI_PMU_OVF_CLEAR_PENDING() macros, respectively. To make use of Andes PMU extension, "xandespmu" needs to be appended to the riscv,isa-extensions for each cpu node in device-tree, and make sure CONFIG_ANDES_CUSTOM_PMU is enabled. Signed-off-by:
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Yu Chien Peter Lin authored
The interrupt enable/disable operations are already performed by the IRQ chip functions riscv_intc_irq_unmask()/riscv_intc_irq_mask() during enable_percpu_irq()/disable_percpu_irq(). It can be done only once. Signed-off-by:
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Yu Chien Peter Lin authored
The Andes hart-level interrupt controller (Andes INTC) allows AX45MP cores to handle custom local interrupts, such as the performance counter overflow interrupt. Signed-off-by:
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Yu Chien Peter Lin authored
Add "andestech,cpu-intc" compatible string to indicate that Andes specific local interrupt is supported on the core, e.g. AX45MP cores have 3 types of non-standard local interrupt which can be handled in supervisor mode: - Slave port ECC error interrupt - Bus write transaction error interrupt - Performance monitor overflow interrupt These interrupts are enabled/disabled via a custom register SLIE instead of the standard interrupt enable register SIE. Signed-off-by:
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Yu Chien Peter Lin authored
Use "ANDES" rather than "ANDESTECH" to unify the naming convention with directory, file names, Kconfig options and other definitions. Signed-off-by:
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Palmer Dabbelt authored
Merge tag 'irq-for-riscv-02-23-24' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tip/tip into for-next INTC changes to consume for RISCV * tag 'irq-for-riscv-02-23-24' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/riscv-intc: Introduce Andes hart-level interrupt controller irqchip/riscv-intc: Allow large non-standard interrupt number
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- 29 Feb, 2024 2 commits
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Alexandre Ghiti authored
pte_leaf_size() must be reimplemented to add support for NAPOT mappings. Fixes: 82a1a1f3 ("riscv: mm: support Svnapot in hugetlb page") Signed-off-by:
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Alexandre Ghiti authored
This reverts commit ce173474. We cannot correctly deal with NAPOT mappings in vmalloc/vmap because if some part of a NAPOT mapping is unmapped, the remaining mapping is not updated accordingly. For example: ptr = vmalloc_huge(64 * 1024, GFP_KERNEL); vunmap_range((unsigned long)(ptr + PAGE_SIZE), (unsigned long)(ptr + 64 * 1024)); leads to the following kernel page table dump: 0xffff8f8000ef0000-0xffff8f8000ef1000 0x00000001033c0000 4K PTE N .. .. D A G . . W R V Meaning the first entry which was not unmapped still has the N bit set, which, if accessed first and cached in the TLB, could allow access to the unmapped range. That's because the logic to break the NAPOT mapping does not exist and likely won't. Indeed, to break a NAPOT mapping, we first have to clear the whole mapping, flush the TLB and then set the new mapping ("break- before-make" equivalent). That works fine in userspace since we can handle any pagefault occurring on the remaining mapping but we can't handle a kernel pagefault on such mapping. So fix this by reverting the commit that introduced the vmap/vmalloc support. Fixes: ce173474 ("riscv: mm: support Svnapot in huge vmap") Signed-off-by:
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- 28 Feb, 2024 2 commits
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Eric Biggers authored
LLVM commit 8e01042da9d3 ("[RISCV] Add missing dependency check for Zvkb (#79467)") broke the check used by the TOOLCHAIN_HAS_VECTOR_CRYPTO kconfig symbol because it made zvkb start depending on v or zve*. Fix this by specifying both v and zvkb when checking for support for zvkb. Signed-off-by:Eric Biggers <ebiggers@google.com> Reviewed-by:
Nathan Chancellor <nathan@kernel.org> Reviewed-by:
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Palmer Dabbelt authored
These fixes are a dependency for the Zvkb patches, so I'm merging them into for-next as well as fixes. * commit '3aff0c45': RISC-V: Drop invalid test from CONFIG_AS_HAS_OPTION_ARCH kbuild: Add -Wa,--fatal-warnings to as-instr invocation
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- 23 Feb, 2024 2 commits
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Yu Chien Peter Lin authored
Add support for the Andes hart-level interrupt controller. This controller provides interrupt mask/unmask functions to access the custom register (SLIE) where the non-standard S-mode local interrupt enable bits are located. The base of custom interrupt number is set to 256. To share the riscv_intc_domain_map() with the generic RISC-V INTC and ACPI, add a chip parameter to riscv_intc_init_common(), so it can be passed to the irq_domain_set_info() as a private data. Andes hart-level interrupt controller requires the "andestech,cpu-intc" compatible string to be present in interrupt-controller of cpu node to enable the use of custom local interrupt source. e.g., cpu0: cpu@0 { compatible = "andestech,ax45mp", "riscv"; ... cpu0-intc: interrupt-controller { #interrupt-cells = <0x01>; compatible = "andestech,cpu-intc", "riscv,cpu-intc"; interrupt-controller; }; }; Signed-off-by:Thomas Gleixner <tglx@linutronix.de> Reviewed-by:
Randolph <randolph@andestech.com> Reviewed-by:
Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20240222083946.3977135-4-peterlin@andestech.com
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Yu Chien Peter Lin authored
Currently, the implementation of the RISC-V INTC driver uses the interrupt cause as the hardware interrupt number, with a maximum of 64 interrupts. However, the platform can expand the interrupt number further for custom local interrupts. To fully utilize the available local interrupt sources, switch to using irq_domain_create_tree() that creates the radix tree map, add global variables (riscv_intc_nr_irqs, riscv_intc_custom_base and riscv_intc_custom_nr_irqs) to determine the valid range of local interrupt number (hwirq). Signed-off-by:
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- 17 Feb, 2024 2 commits
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Nathan Chancellor authored
Commit e4bb020f ("riscv: detect assembler support for .option arch") added two tests, one for a valid value to '.option arch' that should succeed and one for an invalid value that is expected to fail to make sure that support for '.option arch' is properly detected because Clang does not error when '.option arch' is not supported: $ clang --target=riscv64-linux-gnu -Werror -x assembler -c -o /dev/null <(echo '.option arch, +m') /dev/fd/63:1:9: warning: unknown option, expected 'push', 'pop', 'rvc', 'norvc', 'relax' or 'norelax' .option arch, +m ^ $ echo $? 0 Unfortunately, the invalid test started being accepted by Clang after the linked llvm-project change, which causes CONFIG_AS_HAS_OPTION_ARCH and configurations that depend on it to be silently disabled, even though those versions do support '.option arch'. The invalid test can be avoided altogether by using '-Wa,--fatal-warnings', which will turn all assembler warnings into errors, like '-Werror' does for the compiler: $ clang --target=riscv64-linux-gnu -Werror -Wa,--fatal-warnings -x assembler -c -o /dev/null <(echo '.option arch, +m') /dev/fd/63:1:9: error: unknown option, expected 'push', 'pop', 'rvc', 'norvc', 'relax' or 'norelax' .option arch, +m ^ $ echo $? 1 The as-instr macros have been updated to make use of this flag, so remove the invalid test, which allows CONFIG_AS_HAS_OPTION_ARCH to work for all compiler versions. Cc: stable@vger.kernel.org Fixes: e4bb020f ("riscv: detect assembler support for .option arch") Link: https://github.com/llvm/llvm-project/commit/3ac9fe69f70a2b3541266daedbaaa7dc9c007a2aReported-by:
Eric Biggers <ebiggers@kernel.org> Closes: https://lore.kernel.org/r/20240121011341.GA97368@sol.localdomain/Signed-off-by:
Andy Chiu <andybnac@gmail.com> Reviewed-by:
Masahiro Yamada <masahiroy@kernel.org> Link: https://lore.kernel.org/r/20240125-fix-riscv-option-arch-llvm-18-v1-2-390ac9cc3cd0@kernel.orgSigned-off-by:
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Nathan Chancellor authored
Certain assembler instruction tests may only induce warnings from the assembler on an unsupported instruction or option, which causes as-instr to succeed when it was expected to fail. Some tests workaround this limitation by additionally testing that invalid input fails as expected. However, this is fragile if the assembler is changed to accept the invalid input, as it will cause the instruction/option to be unavailable like it was unsupported even when it is. Use '-Wa,--fatal-warnings' in the as-instr macro to turn these warnings into hard errors, which avoids this fragility and makes tests more robust and well formed. Cc: stable@vger.kernel.org Suggested-by:
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- 16 Feb, 2024 1 commit
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Drew Fustini authored
Enable the mmc controller driver and dma controller driver needed for T-Head TH1520 based boards, like the LicheePi 4A and BeagleV-Ahead, to boot from eMMC storage. Reviewed-by:
Guo Ren <guoren@kernel.org> Signed-off-by:
Drew Fustini <dfustini@baylibre.com> Reviewed-by:
Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by:
Jisheng Zhang <jszhang@kernel.org> Link: https://lore.kernel.org/r/20231206-th1520_mmc_dts-v8-1-69220e373e8f@baylibre.comSigned-off-by:
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- 15 Feb, 2024 5 commits
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Palmer Dabbelt authored
RISC-V was lacking a membarrier implementation for the store/fetch ordering, which is a bit tricky because of the deferred icache flushing we use in RISC-V. * b4-shazam-merge: membarrier: riscv: Provide core serializing command locking: Introduce prepare_sync_core_cmd() membarrier: Create Documentation/scheduler/membarrier.rst membarrier: riscv: Add full memory barrier in switch_mm() Link: https://lore.kernel.org/r/20240131144936.29190-1-parri.andrea@gmail.comSigned-off-by:
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Andrea Parri authored
RISC-V uses xRET instructions on return from interrupt and to go back to user-space; the xRET instruction is not core serializing. Use FENCE.I for providing core serialization as follows: - by calling sync_core_before_usermode() on return from interrupt (cf. ipi_sync_core()), - via switch_mm() and sync_core_before_usermode() (respectively, for uthread->uthread and kthread->uthread transitions) before returning to user-space. On RISC-V, the serialization in switch_mm() is activated by resetting the icache_stale_mask of the mm at prepare_sync_core_cmd(). Suggested-by:
Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by:
Andrea Parri <parri.andrea@gmail.com> Reviewed-by:
Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Link: https://lore.kernel.org/r/20240131144936.29190-5-parri.andrea@gmail.comSigned-off-by:
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Andrea Parri authored
Introduce an architecture function that architectures can use to set up ("prepare") SYNC_CORE commands. The function will be used by RISC-V to update its "deferred icache- flush" data structures (icache_stale_mask). Architectures defining prepare_sync_core_cmd() static inline need to select ARCH_HAS_PREPARE_SYNC_CORE_CMD. Suggested-by: -
Andrea Parri authored
To gather the architecture requirements of the "private/global expedited" membarrier commands. The file will be expanded to integrate further information about the membarrier syscall (as needed/desired in the future). While at it, amend some related inline comments in the membarrier codebase. Suggested-by:
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Andrea Parri authored
The membarrier system call requires a full memory barrier after storing to rq->curr, before going back to user-space. The barrier is only needed when switching between processes: the barrier is implied by mmdrop() when switching from kernel to userspace, and it's not needed when switching from userspace to kernel. Rely on the feature/mechanism ARCH_HAS_MEMBARRIER_CALLBACKS and on the primitive membarrier_arch_switch_mm(), already adopted by the PowerPC architecture, to insert the required barrier. Fixes: fab957c1 ("RISC-V: Atomic and Locking Code") Signed-off-by:
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- 25 Jan, 2024 3 commits
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Xiao Wang authored
There's code duplication between the fallback implementation for bitops __ffs/__fls/ffs/fls API and the generic C implementation in include/asm-generic/bitops/. To avoid this duplication, this patch renames the generic C implementation by adding a "generic_" prefix to them, then we can use these generic APIs as fallback. Suggested-by:
Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by:
Xiao Wang <xiao.w.wang@intel.com> Reviewed-by:
Charlie Jenkins <charlie@rivosinc.com> Link: https://lore.kernel.org/r/20231112094421.4014931-1-xiao.w.wang@intel.comSigned-off-by:
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Song Shuai authored
Inspired from arm64's implement -- commit 70918779 ("arm64: entry: Enable random_kstack_offset support") Add support of kernel stack offset randomization while handling syscall, the offset is defaultly limited by KSTACK_OFFSET_MAX() (i.e. 10 bits). In order to avoid trigger stack canaries (due to __builtin_alloca) and slowing down the entry path, use __no_stack_protector attribute to disable stack protector for do_trap_ecall_u() at the function level. Acked-by:
Kees Cook <keescook@chromium.org> Signed-off-by:
Song Shuai <songshuaishuai@tinylab.org> Link: https://lore.kernel.org/r/20231109133751.212079-1-songshuaishuai@tinylab.orgSigned-off-by:
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Yang Li authored
./arch/riscv/kernel/smpboot.c: asm/cpufeature.h is included more than once. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=7086Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/20231031004018.45074-1-yang.lee@linux.alibaba.comSigned-off-by:
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- 24 Jan, 2024 9 commits
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Clément Léger authored
Adding kprobes on some assembly functions (mainly exception handling) will result in crashes (either recursive trap or panic). To avoid such errors, add ASM_NOKPROBE() macro which allow adding specific symbols into the __kprobe_blacklist section and use to blacklist the following symbols that showed to be problematic: - handle_exception() - ret_from_exception() - handle_kernel_stack_overflow() Signed-off-by:
Clément Léger <cleger@rivosinc.com> Reviewed-by:
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Palmer Dabbelt authored
Jisheng Zhang <jszhang@kernel.org> says: This series adds fast gup support to riscv. The First patch fixes a bug in __p*d_free_tlb(). Per the riscv privileged spec, if non-leaf PTEs I.E pmd, pud or p4d is modified, a sfence.vma is a must. The 2nd patch is a preparation patch. The last two patches do the real work: In order to implement fast gup we need to ensure that the page table walker is protected from page table pages being freed from under it. riscv situation is more complicated than other architectures: some riscv platforms may use IPI to perform TLB shootdown, for example, those platforms which support AIA, usually the riscv_ipi_for_rfence is true on these platforms; some riscv platforms may rely on the SBI to perform TLB shootdown, usually the riscv_ipi_for_rfence is false on these platforms. To keep software pagetable walkers safe in this case we switch to RCU based table free (MMU_GATHER_RCU_TABLE_FREE). See the comment below 'ifdef CONFIG_MMU_GATHER_RCU_TABLE_FREE' in include/asm-generic/tlb.h for more details. This patch enables MMU_GATHER_RCU_TABLE_FREE, then use *tlb_remove_page_ptdesc() for those platforms which use IPI to perform TLB shootdown; *tlb_remove_ptdesc() for those platforms which use SBI to perform TLB shootdown; Both case mean that disabling interrupts will block the free and protect the fast gup page walker. So after the 3rd patch, everything is well prepared, let's select HAVE_FAST_GUP if MMU. * b4-shazam-merge: riscv: enable HAVE_FAST_GUP if MMU riscv: enable MMU_GATHER_RCU_TABLE_FREE for SMP && MMU riscv: tlb: convert __p*d_free_tlb() to inline functions riscv: tlb: fix __p*d_free_tlb() Link: https://lore.kernel.org/r/20231219175046.2496-1-jszhang@kernel.orgSigned-off-by:
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Jisheng Zhang authored
Activate the fast gup for riscv mmu platforms. Here are some GUP_FAST_BENCHMARK performance numbers: Before the patch: GUP_FAST_BENCHMARK: Time: get:53203 put:5085 us After the patch: GUP_FAST_BENCHMARK: Time: get:17711 put:5060 us The get time is reduced by 66.7%! IOW, 3x get speed! Signed-off-by:
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Jisheng Zhang authored
In order to implement fast gup we need to ensure that the page table walker is protected from page table pages being freed from under it. riscv situation is more complicated than other architectures: some riscv platforms may use IPI to perform TLB shootdown, for example, those platforms which support AIA, usually the riscv_ipi_for_rfence is true on these platforms; some riscv platforms may rely on the SBI to perform TLB shootdown, usually the riscv_ipi_for_rfence is false on these platforms. To keep software pagetable walkers safe in this case we switch to RCU based table free (MMU_GATHER_RCU_TABLE_FREE). See the comment below 'ifdef CONFIG_MMU_GATHER_RCU_TABLE_FREE' in include/asm-generic/tlb.h for more details. This patch enables MMU_GATHER_RCU_TABLE_FREE, then use *tlb_remove_page_ptdesc() for those platforms which use IPI to perform TLB shootdown; *tlb_remove_ptdesc() for those platforms which use SBI to perform TLB shootdown; Both case mean that disabling interrupts will block the free and protect the fast gup page walker. Signed-off-by:
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Jisheng Zhang authored
This is to prepare for enabling MMU_GATHER_RCU_TABLE_FREE. No functionality changes. Signed-off-by:
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Jisheng Zhang authored
If non-leaf PTEs I.E pmd, pud or p4d is modified, a sfence.vma is a must for safe, imagine if an implementation caches the non-leaf translation in TLB, although I didn't meet this HW so far, but it's possible in theory. Signed-off-by:
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Palmer Dabbelt authored
Sami Tolvanen <samitolvanen@google.com> says: We noticed that 64-bit RISC-V kernels limit mmap_rnd_bits to 24 even if the hardware supports a larger virtual address space size [1]. These two patches allow mmap_rnd_bits_max to be changed during init, and bumps up the maximum randomness if we end up setting up 4/5-level paging at boot. * b4-shazam-merge: riscv: mm: Update mmap_rnd_bits_max mm: Change mmap_rnd_bits_max to __ro_after_init Link: https://lore.kernel.org/r/20230929211155.3910949-4-samitolvanen@google.comSigned-off-by:
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Sami Tolvanen authored
ARCH_MMAP_RND_BITS_MAX is based on Sv39, which leaves a few potential bits of mmap randomness on the table if we end up enabling 4/5-level paging. Update mmap_rnd_bits_max to take the final address space size into account. This increases mmap_rnd_bits_max from 24 to 33 with Sv48/57. Signed-off-by:
Sami Tolvanen <samitolvanen@google.com> Reviewed-by:
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Sami Tolvanen authored
Allow mmap_rnd_bits_max to be updated on architectures that determine virtual address space size at runtime instead of relying on Kconfig options by changing it from const to __ro_after_init. Signed-off-by:
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- 23 Jan, 2024 2 commits
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Conor Dooley authored
Revert commit ed309ce5 ("RISC-V: mark hibernation as nonportable") as it appears the broken versions of OpenSBI have not made it to production on any systems that support hibernation. Signed-off-by:
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Vincent Chen authored
When registering the riscv-timer or clint-timer as a clock_event device, the driver needs to specify the value of max_delta_ticks. This value directly influences the max_delta_ns, which represents the maximum time interval for configuring subsequent clock events. Currently, both riscv-timer and clint-timer are set with a max_delta_ticks value of 0x7fff_ffff. When the timer operates at a high frequency, this values limists the system to sleep only for a short time. For the 1GHz case, the sleep cannot exceed two seconds. To address this limitation, refer to other timer implementations to extend it to 2^(bit-width of the timer) - 1. Because the bit-width of $mtimecmp is 64bit, this value becomes ULONG_MAX (0xffff_ffff_ffff_ffff). Signed-off-by:
Vincent Chen <vincent.chen@sifive.com> Link: https://lore.kernel.org/r/20230905070945.404653-1-vincent.chen@sifive.comSigned-off-by:
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