- 26 Sep, 2018 2 commits
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John Garry authored
Currently the driver overwrites the surface depth provided by the fb helper to give an invalid bpp/surface depth combination. This has been exposed by commit 70109354 ("drm: Reject unknown legacy bpp and depth for drm_mode_addfb ioctl"), which now causes the driver to fail to probe. Fix by not overwriting the surface depth. Fixes: d1667b86 ("drm/hisilicon/hibmc: Add support for frame buffer") Signed-off-by:
John Garry <john.garry@huawei.com> Reviewed-by:
Xinliang Liu <z.liuxinliang@hisilicon.com> Signed-off-by:
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John Garry authored
In hibmc_drm_fb_create(), when the call to hibmc_framebuffer_init() fails with error, do not store the error code in the HiBMC device frame-buffer pointer, as this will be later checked for non-zero value in hibmc_fbdev_destroy() when our intention is to check for a valid function pointer. This fixes the following crash: [ 9.699791] Unable to handle kernel NULL pointer dereference at virtual address 000000000000001a [ 9.708672] Mem abort info: [ 9.711489] ESR = 0x96000004 [ 9.714570] Exception class = DABT (current EL), IL = 32 bits [ 9.720551] SET = 0, FnV = 0 [ 9.723631] EA = 0, S1PTW = 0 [ 9.726799] Data abort info: [ 9.729702] ISV = 0, ISS = 0x00000004 [ 9.733573] CM = 0, WnR = 0 [ 9.736566] [000000000000001a] user address but active_mm is swapper [ 9.742987] Internal error: Oops: 96000004 [#1] PREEMPT SMP [ 9.748614] Modules linked in: [ 9.751694] CPU: 16 PID: 293 Comm: kworker/16:1 Tainted: G W 4.19.0-rc4-next-20180920-00001-g9b0012c #322 [ 9.762681] Hardware name: Huawei Taishan 2280 /D05, BIOS Hisilicon D05 IT21 Nemo 2.0 RC0 04/18/2018 [ 9.771915] Workqueue: events work_for_cpu_fn [ 9.776312] pstate: 60000005 (nZCv daif -PAN -UAO) [ 9.781150] pc : drm_mode_object_put+0x0/0x20 [ 9.785547] lr : hibmc_fbdev_fini+0x40/0x58 [ 9.789767] sp : ffff00000af1bcf0 [ 9.793108] x29: ffff00000af1bcf0 x28: 0000000000000000 [ 9.798473] x27: 0000000000000000 x26: ffff000008f66630 [ 9.803838] x25: 0000000000000000 x24: ffff0000095abb98 [ 9.809203] x23: ffff8017db92fe00 x22: ffff8017d2b13000 [ 9.814568] x21: ffffffffffffffea x20: ffff8017d2f80018 [ 9.819933] x19: ffff8017d28a0018 x18: ffffffffffffffff [ 9.825297] x17: 0000000000000000 x16: 0000000000000000 [ 9.830662] x15: ffff0000092296c8 x14: ffff00008939970f [ 9.836026] x13: ffff00000939971d x12: ffff000009229940 [ 9.841391] x11: ffff0000085f8fc0 x10: ffff00000af1b9a0 [ 9.846756] x9 : 000000000000000d x8 : 6620657a696c6169 [ 9.852121] x7 : ffff8017d3340580 x6 : ffff8017d4168000 [ 9.857486] x5 : 0000000000000000 x4 : ffff8017db92fb20 [ 9.862850] x3 : 0000000000002690 x2 : ffff8017d3340480 [ 9.868214] x1 : 0000000000000028 x0 : 0000000000000002 [ 9.873580] Process kworker/16:1 (pid: 293, stack limit = 0x(____ptrval____)) [ 9.880788] Call trace: [ 9.883252] drm_mode_object_put+0x0/0x20 [ 9.887297] hibmc_unload+0x1c/0x80 [ 9.890815] hibmc_pci_probe+0x170/0x3c8 [ 9.894773] local_pci_probe+0x3c/0xb0 [ 9.898555] work_for_cpu_fn+0x18/0x28 [ 9.902337] process_one_work+0x1e0/0x318 [ 9.906382] worker_thread+0x228/0x450 [ 9.910164] kthread+0x128/0x130 [ 9.913418] ret_from_fork+0x10/0x18 [ 9.917024] Code: a94153f3 a8c27bfd d65f03c0 d503201f (f9400c01) [ 9.923180] ---[ end trace 2695ffa0af5be375 ]--- Fixes: d1667b86 ("drm/hisilicon/hibmc: Add support for frame buffer") Signed-off-by:
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- 20 Sep, 2018 5 commits
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
This is a new pull for drm-next on top of last weeks with the following changes: - Fixed 64 bit divide - Fixed vram type on vega20 - Misc vega20 fixes - Misc DC fixes - Fix GDS/GWS/OA domain handling Previous changes from last week: amdgpu/kfd: - Picasso (new APU) support - Raven2 (new APU) support - Vega20 enablement - ACP powergating improvements - Add ABGR/XBGR display support - VCN JPEG engine support - Initial xGMI support - Use load balancing for engine scheduling - Lots of new documentation - Rework and clean up i2c and aux handling in DC - Add DP YCbCr 4:2:0 support in DC - Add DMCU firmware loading for Raven (used for ABM and PSR) - New debugfs features in DC - LVDS support in DC - Implement wave kill for gfx/compute (light weight reset for shaders) - Use AGP aperture to avoid gart mappings when possible - GPUVM performance improvements - Bulk moves for more efficient GPUVM LRU handling - Merge amdgpu and amdkfd into one module - Enable gfxoff and stutter mode on Raven - Misc cleanups Scheduler: - Load balancing support - Bug fixes ttm: - Bulk move functionality - Bug fixes radeon: - Misc cleanups Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180920150438.12693-1-alexander.deucher@amd.com
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git://linuxtv.org/pinchartl/mediaDave Airlie authored
R-Car DU changes for v4.20 The pull request mostly contains updates to the R-Car DU driver, notably support for interlaced modes on Gen3 hardware, support for the LVDS output on R8A77980, and a set of miscellaneous bug fixes. There are also two SPDX conversion patches for the drm shmobile and panel-lvds drivers, as well as an update to MAINTAINERS to add Kieran Bingham as a co-maintainer for the DU driver. Signed-off-by:
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Frank Min authored
Temporary disable UVD/VCE block if is virtual device Signed-off-by:
Frank Min <Frank.Min@amd.com> Signed-off-by:
Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Frank Min authored
Add sriov capability detection for vega20, then can check if device is virtual device. Signed-off-by:
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git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
drm-misc-next for 4.20: UAPI Changes: - None Cross-subsystem Changes: - None Core Changes: - Allow drivers to disable features with per-device granularity (Ville) - Use EOPNOTSUPP when iface/feature is unsupported instead of EINVAL/errno soup (Chris) - Simplify M/N DP quirk by using constant N to limit size of M/N (Shawn) - add quirk for LG LP140WF6-SPM1 eDP panel (Shawn) Driver Changes: - i915/amdgpu: Disable DRIVER_ATOMIC for older/unsupported devices (Ville) - sun4i: add support for R40 HDMI PHY (Icenowy) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Icenowy Zheng <icenowy@aosc.io> Cc: Lee, Shawn C <shawn.c.lee@intel.com> Signed-off-by:
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- 19 Sep, 2018 29 commits
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Christian König authored
We don't need that in the per ASIC code. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Christian König authored
Stops crashing on SI. Signed-off-by:
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Christian König authored
That only worked by pure coincident. Completely remove the shifting and always apply correct PAGE_SHIFT. Signed-off-by:
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Christian König authored
Don't grab the reservation lock any more and simplify the handling quite a bit. Signed-off-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Christian König authored
It shouldn't add much overhead and we should make sure that critical VRAM content is always restored. Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by:
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Christian König authored
They aren't directly used by the hardware. Signed-off-by:
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Christian König authored
Even when GPU recovery is disabled we could run into a manually triggered recovery. v2: keep accidental removed comments Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
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Christian König authored
We are going to need this for recoverable page fault handling and it makes shadow handling during GPU reset much more easier. Signed-off-by:
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Christian König authored
DC doesn't seem to have a fallback path either. So when interrupts doesn't work any more we are pretty much busted no matter what. Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
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Evan Quan authored
With OD settings applied, the clock table will be updated accordingly. We need to retrieve the new clock tables then. Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
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Evan Quan authored
With the latest SMC fw, we are able to get the voltage value for specific frequency point. So, we update the OD relates to take absolute voltage instead of offset. Signed-off-by:
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Evan Quan authored
Update the conditions to judge whether an OD feature should be supported on vega20. Signed-off-by:
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Hawking Zhang authored
vega20 should use umc_info v3_3 instead of v3_1. There are serveral versions of umc_info for vega series. Compared to various versions of these structures, vram_info strucure is unified for vega series. The patch switch to query mem_type from vram_info structure for all the vega series dGPU. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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Hawking Zhang authored
atomfirmware has structure changes in varm_info. Updated it to the latest one. Signed-off-by:
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Mathieu Malaterre authored
In function ‘radeon_process_i2c_ch’ a comparison of a u8 value against 255 is done. Since it is always false, change the signature of this function to use an `int` instead, which match the type used in caller: `radeon_atom_hw_i2c_xfer`. Fix the following warning triggered with W=1: CC [M] drivers/gpu/drm/radeon/atombios_i2c.o drivers/gpu/drm/radeon/atombios_i2c.c: In function ‘radeon_process_i2c_ch’: drivers/gpu/drm/radeon/atombios_i2c.c:71:11: warning: comparison is always false due to limited range of data type [-Wtype-limits] if (num > ATOM_MAX_HW_I2C_READ) { ^ Reviewed-by:Mathieu Malaterre <malat@debian.org> Signed-off-by:
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A. Wilcox authored
adev->gfx.rlc has the values from rlc_hdr already processed by le32_to_cpu. Using the rlc_hdr values on big-endian machines causes a kernel Oops due to writing well outside of the array (0x24000000 instead of 0x24). Signed-off-by:
A. Wilcox <AWilcox@Wilcox-Tech.com> Signed-off-by:
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Tom St Denis authored
Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Christian König authored
We no don't allocate zero sized kernel BOs any longer. Signed-off-by:
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Christian König authored
Just free the BO if the size should be zero. Signed-off-by:
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Christian König authored
Simply ignore any copying here. Signed-off-by:
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Christian König authored
Additional to the existing files for VRAM and GTT. Signed-off-by:
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Christian König authored
The function was modified without updating the documentation. Signed-off-by:
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Christian König authored
We can't get the mask for the root directory from the number of entries. So add a new function to avoid that problem. v2: fix typo in mask Signed-off-by:
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Lee, Shawn C authored
The N value was computed by kernel driver that based on synchronous clock mode. But only specific N value (0x8000) would be acceptable for LG LP140WF6-SPM1 eDP panel which is running at asynchronous clock mode. With the other N value, Tcon will enter BITS mode and display black screen. Add this panel into quirk database and give particular N value when calculate M/N divider. v2: no update v3: add lost commit messages back for version 2 v4: send patch to both intel-gfx and dri-devel Cc: Jani Nikula <jani.nikula@intel.com> Cc: Cooper Chiou <cooper.chiou@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Clint Taylor <clinton.a.taylor@intel.com> Signed-off-by:
Lee, Shawn C <shawn.c.lee@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1536733371-25004-4-git-send-email-shawn.c.lee@intel.com
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Lee, Shawn C authored
Some DP dongles in particular seem to be fussy about too large link M/N values. Set specific value for N divider can resolve this issue per dongle vendor's comment. So configure N as constant value (0x8000) to instead of reduce M/N formula when specific DP dongle connected. v2: add more comments for issue description and fix typo. v3: add lost commit messages back for version 2 v4: send patch to both intel-gfx and dri-devel Cc: Jani Nikula <jani.nikula@intel.com> Cc: Cooper Chiou <cooper.chiou@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Clint Taylor <clinton.a.taylor@intel.com> Tested-by:
Clint Taylor <clinton.a.taylor@intel.com> Signed-off-by:
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Lee, Shawn C authored
DP quirk list just compare sink or branch device's OUI so far. That means particular vendor's products will be applied specific change. This change would confirm device_id the same or not. Then driver can implement some changes for branch/sink device that really need additional WA. v2: use sizeof instead of hard coded '6' v3: add lost commit messages back for version 2 v4: send patch to both intel-gfx and dri-devel Cc: Jani Nikula <jani.nikula@intel.com> Cc: Cooper Chiou <cooper.chiou@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Clint Taylor <clinton.a.taylor@intel.com> Tested-by:
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Jiandi An authored
With virtio gpu ttm-pages being dma mapped, dma sync is needed when swiotlb is used as bounce buffers, before TRANSFER_TO_HOST_2D/3D commands are sent. Signed-off-by:
Jiandi An <jiandi.an@amd.com> Link: http://patchwork.freedesktop.org/patch/msgid/20180919070931.91168-1-jiandi.an@amd.comSigned-off-by:
Gerd Hoffmann <kraxel@redhat.com>
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Icenowy Zheng authored
The R40 SoC has a HDMI PHY that is possible to mux two video PLLs. Add support for it. Signed-off-by:
Icenowy Zheng <icenowy@aosc.io> Signed-off-by:
Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180916043409.62374-4-icenowy@aosc.io
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Icenowy Zheng authored
The Allwinner R40 HDMI PHY is currently the only one that seems to be able to select between two PLL inputs. Add a compatible string for it, and the pll-1 clock input definition. Signed-off-by:
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- 15 Sep, 2018 4 commits
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Kieran Bingham authored
The Gen3 VSP used by the DU for display does not support the packed VYUY pixel format. Gen2 VSP hardware is able to process this format, but DU + VSP operation isn't enabled on Gen2, and VYUY isn't a strategic format, so it can be ignored. Remove the format from the capabilities of the DU driver. Signed-off-by:
Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
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Laurent Pinchart authored
The framebuffer pitch and alignment constraints reflect the limitations of the Gen2 DU hardware. On Gen3, the DU has no memory interface and thus doesn't impose any constraint. The limitations come instead from the VSP that has a limit of 65535 bytes for the pitch and no alignment constraint. Update the checks accordingly. Signed-off-by:
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Koji Matsuoka authored
This patch supports pixel format of RGB332, ARGB4444, XRGB4444, BGR888, RGB888, BGRA8888, BGRX8888 and YVYU. VYUY pixel format is not supported by H/W specification. Signed-off-by:
Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by:
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Kieran Bingham authored
The R-Car Gen3 DU utilises the VSP1 hardware for memory access. The limits on the RPF and WPF in this pipeline are 8190x8190. Update the supported maximum sizes accordingly. Signed-off-by:
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