- 08 Oct, 2014 1 commit
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Paulo Zanoni authored
We were missing the pipe B/C vblank bits! Take a look at gen8_de_irq_postinstall for a comparison. This should fix a bunch of IGT tests. There are a few more things we could improve on this code, but this should be the minimal fix to unblock us. v2: s/extra_iir/extra_ier/ because IIR doesn't make sense (Ville) Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=83640 Testcase: igt/* Cc: stable@vger.kernel.org Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com>
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- 06 Oct, 2014 2 commits
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U. Artie Eoff authored
Move the duplicated DIV_ROUND_CLOSEST_ULL macro into the intel_drv.h header file so that it can be shared between intel_display.c and intel_panel.c. Signed-off-by:
U. Artie Eoff <ullysses.a.eoff@intel.com> Reviewed-By:
Joe Konno <joe.konno@intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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U. Artie Eoff authored
Improper truncated integer division in the scale() function causes actual_brightness != brightness. This (partial) work-around should be sufficient for a majority of use-cases, but it is by no means a complete solution. TODO: Determine how best to scale "user" values to "hw" values, and vice-versa, when the ranges are of different sizes. That would be a buggy scenario even with this work-around. The issue was introduced in the following (v3.17-rc1) commit: 6dda730e drm/i915: respect the VBT minimum backlight brightness Note that for easier backporting this commit adds a duplicated macro. A follow-up cleanup patch rectifies this for 3.18+ v2: (thanks to Chris Wilson) clarify commit message, use rounded division macro v3: -DIV_ROUND_CLOSEST() fails to build with CONFIG_X86_32=y. (Jani) -Use DIV_ROUND_CLOSEST_ULL() instead. (Damien) -v1 and v2 originally authored by Joe Konno. Signed-off-by:
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- 01 Oct, 2014 1 commit
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Clint Taylor authored
Haswell and later silicon has added a new pixel replication register to the pipe timings for each transcoder. Now in addition to the DPLL_A_MD register for the pixel clock double, we also need to write to the TRANS_MULT_n (0x6002c) register to double the pixel data. Writing to the DPLL only double the pixel clock. ver2: Macro name change from MULTIPLY to PIPE_MULTI. (Daniel) ver3: Do not set pixel multiplier if transcoder is eDP (Ville) ver4: Macro name change to PIPE_MULT and default else pixel_multiplier Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
Clint Taylor <clinton.a.taylor@intel.com> Reviewed-by:
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- 29 Sep, 2014 4 commits
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Ville Syrjälä authored
If the GPU frequency isn't going to change don't spam dmesg with debug messages about it. Signed-off-by:
Daniel Vetter <daniel.vetter@intel.com>
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Tvrtko Ursulin authored
sg_alloc_table_from_pages() can build us a table with coalesced ranges which means we need to iterate over pages and not sg table entries when releasing page references. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: "Barbalho, Rafael" <rafael.barbalho@intel.com> Tested-by:
Rafael Barbalho <rafael.barbalho@intel.com> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@vger.kernel.org [danvet: Remove unused local variable sg.] Signed-off-by:
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Chris Wilson authored
If we fail to create our mmu notification, we report the error back and currently store the error inside the i915_mm_struct. This not only causes subsequent registerations of the same mm to fail (an issue if the first was interrupted by a signal and needed to be restarted) but also causes us to eventually try and free the error pointer. [ 73.419599] BUG: unable to handle kernel NULL pointer dereference at 000000000000004c [ 73.419831] IP: [<ffffffff8114af33>] mmu_notifier_unregister+0x23/0x130 [ 73.420065] PGD 8650c067 PUD 870bb067 PMD 0 [ 73.420319] Oops: 0000 [#1] SMP DEBUG_PAGEALLOC [ 73.420580] CPU: 0 PID: 42 Comm: kworker/0:1 Tainted: G W 3.17.0-rc6+ #1561 [ 73.420837] Hardware name: Intel Corporation SandyBridge Platform/LosLunas CRB, BIOS ASNBCPT1.86C.0075.P00.1106281639 06/28/2011 [ 73.421405] Workqueue: events __i915_mm_struct_free__worker [ 73.421724] task: ffff880088a81220 ti: ffff880088168000 task.ti: ffff880088168000 [ 73.422051] RIP: 0010:[<ffffffff8114af33>] [<ffffffff8114af33>] mmu_notifier_unregister+0x23/0x130 [ 73.422410] RSP: 0018:ffff88008816bd50 EFLAGS: 00010286 [ 73.422765] RAX: 0000000000000003 RBX: ffff880086485400 RCX: 0000000000000000 [ 73.423137] RDX: ffff88016d80ee90 RSI: ffff880086485400 RDI: 0000000000000044 [ 73.423513] RBP: ffff88008816bd70 R08: 0000000000000001 R09: 0000000000000000 [ 73.423895] R10: 0000000000000320 R11: 0000000000000001 R12: 0000000000000044 [ 73.424282] R13: ffff880166e5f008 R14: ffff88016d815200 R15: ffff880166e5f040 [ 73.424682] FS: 0000000000000000(0000) GS:ffff88016d800000(0000) knlGS:0000000000000000 [ 73.425099] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 73.425537] CR2: 000000000000004c CR3: 0000000087f5f000 CR4: 00000000000407f0 [ 73.426157] Stack: [ 73.426597] ffff880088a81248 ffff880166e5f038 fffffffffffffffc ffff880166e5f008 [ 73.427096] ffff88008816bd98 ffffffff814a75f2 ffff880166e5f038 ffff8800880f8a28 [ 73.427603] ffff88016d812ac0 ffff88008816be00 ffffffff8106321a ffffffff810631af [ 73.428119] Call Trace: [ 73.428606] [<ffffffff814a75f2>] __i915_mm_struct_free__worker+0x42/0x80 [ 73.429116] [<ffffffff8106321a>] process_one_work+0x1ba/0x610 [ 73.429632] [<ffffffff810631af>] ? process_one_work+0x14f/0x610 [ 73.430153] [<ffffffff810636db>] worker_thread+0x6b/0x4a0 [ 73.430671] [<ffffffff8108d67d>] ? trace_hardirqs_on+0xd/0x10 [ 73.431501] [<ffffffff81063670>] ? process_one_work+0x610/0x610 [ 73.432030] [<ffffffff8106a206>] kthread+0xf6/0x110 [ 73.432561] [<ffffffff8106a110>] ? __kthread_parkme+0x80/0x80 [ 73.433100] [<ffffffff8169c22c>] ret_from_fork+0x7c/0xb0 [ 73.433644] [<ffffffff8106a110>] ? __kthread_parkme+0x80/0x80 [ 73.434194] Code: 0f 1f 84 00 00 00 00 00 66 66 66 66 90 8b 46 4c 85 c0 0f 8e 10 01 00 00 55 48 89 e5 41 55 41 54 53 48 89 f3 49 89 fc 48 83 ec 08 <48> 83 7f 08 00 0f 84 b1 00 00 00 48 c7 c7 40 e6 ac 82 e8 26 65 [ 73.435942] RIP [<ffffffff8114af33>] mmu_notifier_unregister+0x23/0x130 [ 73.437017] RSP <ffff88008816bd50> [ 73.437704] CR2: 000000000000004c Fixes regression from commit ad46cb53 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Thu Aug 7 14:20:40 2014 +0100 drm/i915: Prevent recursive deadlock on releasing a busy userptr Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84207 Testcase: igt/gem_render_copy_redux Testcase: igt/gem_userptr_blits/create-destroy-sync Signed-off-by:
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Daniel Vetter authored
This reverts commit c76bb61a. It's apparently too broken so that Rodrigo submitted a patch to add a config option for it. Given that the design is also ... suboptimal and that I've only merged this to get lead engineers and managers off my back for one second let's just revert this. /me puts on combat gear again It was worth a shot ... References: http://mid.mail-archive.com/1411686380-1953-1-git-send-email-rodrigo.vivi@intel.com Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Daisy Sun <daisy.sun@intel.com> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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- 24 Sep, 2014 1 commit
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Mika Kuoppala authored
as these have been fixed in production hw and hurt performance if applied. v2: adjust requested ring space (Ville) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83482Tested-by:
zhoujian <jianx.zhou@intel.com> Signed-off-by:
Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by:
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- 19 Sep, 2014 15 commits
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Rodrigo Vivi authored
If something while getting panel CRC this means that probably hw I/O error so hw is busted and try again shouldn't help much. Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Daniel Vetter authored
Based upon a patch from Deepak, but reworked to only apply on gen7+ and with the logic a bit clarified. v2: Fix s/SHIFT/MASK/ fumble that Ville spotted. Cc: Deepak S <deepak.s@intel.com> Reviewed-by:
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Chris Wilson authored
If we believe that the device can cross cache domains in its prefetcher (i.e. we allow neighbouring pages in different domains), we don't supply a color_adjust callback. Use the presence of this callback to better determine when we should be verifying that the GTT space we just used is valid. v2: Remove the superfluous struct drm_device function param as well. Signed-off-by:
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Chris Wilson authored
gen6 and earlier conflate address space selection (ppgtt vs ggtt) with the security bit (i.e. only privileged batches were allowed to run from ggtt). From Haswell only, you are able to select the security bit separate from the address space - and we always requested to use ppgtt. This breaks the golden render state batch execution with full-ppgtt as that is only present in the global GTT and more generally any secure batch that is not colocated in the ppgtt and ggtt. So we need to disable the use of the ppgtt selector bit for secure batches, or else we hang immediately upon boot and thence after every GPU reset... v2: Only HSW differentiates between secure dispatch and ggtt, so simply ignore the differentiation and always use secure==ggtt. Signed-off-by:
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Deepak S authored
In chv, we have two power wells Render & Media. We need to use corresponsing forcewake count. If we dont follow this we are getting error "*ERROR*: Timed out waiting for forcewake old ack to clear" due to multiple entry into __vlv_force_wake_get. Signed-off-by:
Deepak S <deepak.s@linux.intel.com> Requested-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
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Michel Thierry authored
Also here, i915_gem_evict_vm causes an unbind, which can end up dropping the last ref to the ppgtt. Triggered by igt gem_evict_everything test. Testcase: igt/gem_evict_everything Signed-off-by:
Michel Thierry <michel.thierry@intel.com> Reviewed-by:
Chris Wilson <chris@cris-wilsonc.co.uk> Signed-off-by:
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Daniel Vetter authored
Somehow I've overlooked this when simplifying the irq reinit scheme on gen4.5+ in commit 78ad455f Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Thu May 22 22:18:21 2014 +0200 drm/i915: Improve irq handling after gpu resets Since display interrups in general survive a gpu reset on those platforms there's also no need to reinit the hotplug settings. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Chris Wilson authored
drm_send_vblank_event() demands that we hold the event spinlock whilst calling it, so do so. Signed-off-by:
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Chris Wilson authored
Before we process the final unbind on an object and move it to the unbound list, it is semantically cleaner if there are no more active references to the object. (An active reference would imply that it was still being accessed by the GPU after it became inaccessible.) The caveat is that all callsites must be prepared for the object to disappeared during the unbind - i.e. they must hold their own reference. Signed-off-by:
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Chris Wilson authored
Due to the lazy retirement semantics, even though we have unbound an object, it may still hold onto an active reference. So in the debug code, play safe. v2: Export i915_gem_shrink() rather than opencoding it. Signed-off-by:
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Jani Nikula authored
eDP panels are generally designed to support only a single clock and lane configuration. commit 56071a20 Author: Jani Nikula <jani.nikula@intel.com> Date: Tue May 6 14:56:52 2014 +0300 drm/i915: use lane count and link rate from VBT as minimums for eDP should have started using the optimal link parameters for eDP panels. Turns out a certain other OS uses DPCD instead of VBT, which means trusting VBT on this may not be so reliable after all. Follow suit. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81647Tested-by:
Adam Jirasek <libm3l@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79386Tested-by:
Narthana Epa <narthana.epa+freedesktop@gmail.com> Signed-off-by:
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Jani Nikula authored
This goes back to commit 06ea66b6 Author: Todd Previte <tprevite@gmail.com> Date: Mon Jan 20 10:19:39 2014 -0700 drm/i915: Enable 5.4Ghz (HBR2) link rate for Displayport 1.2-capable devices Cc: Todd Previte <tprevite@gmail.com> Signed-off-by:
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Chris Wilson authored
Oops, apparently intel_hdmi/intel_dp is the encoder - an object with a distinct lifetime to the connector, and so we cannot simply reuse the common function to unset and free the edid. Signed-off-by:
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Ville Syrjälä authored
830 is very unhappy of the watermark value is too low (indicating a very high watermark in fact, ie. memory fetch will occur with an almost full FIFO). Limit the watermark value to at least 8 cache lines. That also matches the burst size we use on most platforms. BSpec seems to indicate we should limit the watermark to 'burst size + 1'. But on gen4 we already use a hardcoded 8 as the watermark value (as the spec says we should), so just use 8 as the limit on gen2/3 as well. Signed-off-by:
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Ville Syrjälä authored
The spec says: "For the correct operation of the muxed DVO pins (GDEVSELB/ I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data, GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock Enable) must be set to “1” in both the DPLL A Control Register (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." The pipe A and B force quirks take care of DPLL_VCO_ENABLE, so we just need a bit of special care to handle DPLL_DVO_2X_MODE. v2: Recompute num_dvo_pipes on the spot, use PIPE_A/PIPE_B instead of pipe/!pipe for the register offsets in disable (Daniel) Add a comment about the ordering in enable and another one about filtering out the DVO 2x bit in state readout Signed-off-by:
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- 18 Sep, 2014 1 commit
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git://linuxtv.org/pinchartl/fbdevDave Airlie authored
Commit "drm/rcar-du: Use struct videomode in platform data" touches board code in arch/arm/mach-shmobile. There is, to the best of my knowledge, no risk of conflict for v3.18. Simon, are you fine with getting those changes merged through Dave's tree (and could you confirm that no conflict should occur) ? Simon acked the merge: Acked-by:
Simon Horman <horms+renesas@verge.net.au> * 'drm/next/du' of git://linuxtv.org/pinchartl/fbdev: drm/rcar-du: Add OF support drm/rcar-du: Use struct videomode in platform data video: Add DT bindings for the R-Car Display Unit video: Add THC63LVDM83D DT bindings documentation video: Add ADV7123 DT bindings documentation video: Add DT binding documentation for VGA connector devicetree: Add vendor prefix "thine" to vendor-prefixes.txt devicetree: Add vendor prefix "mitsubishi" to vendor-prefixes.txt drm/shmob: Update copyright notice drm/rcar-du: Update copyright notice
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- 17 Sep, 2014 9 commits
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Kees Cook authored
While zone->name is currently hard coded, the call to kobject_init_and_add() should follow the more defensive argument list usage (as already done in other places in ttm_memory.c) where "%s" is used instead of directly passing in a variable as a format string. Signed-off-by:
Kees Cook <keescook@chromium.org> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Ezequiel Garcia authored
In order to support the "enable GPIO" available in many panel devices, this commit adds a proper devicetree binding. By providing an enable GPIO in the devicetree, the driver can now turn off and on the panel device, and/or the backlight device. Both the backlight and the GPIO are optional properties. Tested-by:
Darren Etheridge <detheridge@ti.com> Tested-by:
Johannes Pointner <johannes.pointner@br-automation.com> Signed-off-by:
Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by:
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Ezequiel Garcia authored
Instead of setting an initial value for the return code, set it explicitly on each error path. This is just a cosmetic cleanup, as preparation for the enable GPIO support. Tested-by:
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Ezequiel Garcia authored
The current backlight support is broken; the driver expects a backlight-class in the panel devicetree node. Fix this by implementing it properly, getting an optional backlight from a phandle. This shouldn't cause any backward-compatibility DT issue because the current implementation doesn't work and is not even documented. Tested-by:
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Ezequiel Garcia authored
Using the managed variant to allocate the resource makes the code simpler and less error-prone. Tested-by:
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Ezequiel Garcia authored
Just a cosmetic cleanup. Tested-by:
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Ezequiel Garcia authored
Just a trivial cleanup to remove the variable. Tested-by:
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Ezequiel Garcia authored
This commit adds the missing calls to of_node_put to release the node that's currently held by the of_get_child_by_name() call in the panel info parsing code. Tested-by:
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Ezequiel Garcia authored
The current error path calls tilcdc_unload() in case of an error to release the resources. However, this is wrong because not all resources have been allocated by the time an error occurs in tilcdc_load(). To fix it, this commit adds proper labels to bail out at the different stages in the load function, and release only the resources actually allocated. Tested-by:
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- 16 Sep, 2014 4 commits
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git://anongit.freedesktop.org/drm-intelDave Airlie authored
- final bits (again) for the rotation support (Sonika Jindal) - support bl_power in the intel backlight (Jani) - vdd handling improvements from Ville - i830M fixes from Ville - piles of prep work all over to make skl enabling just plug in (Damien, Sonika) - rename DP training defines to reflect latest edp standards, this touches all drm drivers supporting DP (Sonika Jindal) - cache edids during single detect cycle to avoid re-reading it for e.g. audio, from Chris - move w/a for registers which are stored in the hw context to the context init code (Arun&Damien) - edp panel power sequencer fixes, helps chv a lot (Ville) - piles of other chv fixes all over - much more paranoid pageflip handling with stall detection and better recovery from Chris - small things all over, as usual * tag 'drm-intel-next-2014-09-05' of git://anongit.freedesktop.org/drm-intel: (114 commits) drm/i915: Update DRIVER_DATE to 20140905 drm/i915: Decouple the stuck pageflip on modeset drm/i915: Check for a stalled page flip after each vblank drm/i915: Introduce a for_each_plane() macro drm/i915: Rewrite ABS_DIFF() in a safer manner drm/i915: Add comments explaining the vdd on/off functions drm/i915: Move DP port disable to post_disable for pch platforms drm/i915: Enable DP port earlier drm/i915: Turn on panel power before doing aux transfers drm/i915: Be more careful when picking the initial power sequencer pipe drm/i915: Reset power sequencer pipe tracking when disp2d is off drm/i915: Track which port is using which pipe's power sequencer drm/i915: Fix edp vdd locking drm/i915: Reset the HEAD pointer for the ring after writing START drm/i915: Fix unsafe vma iteration in i915_drop_caches drm/i915: init sprites with univeral plane init function drm/i915: Check of !HAS_PCH_SPLIT() in PCH transcoder funcs drm/i915: Use HAS_GMCH_DISPLAY un underrun reporting code drm/i915: Use IS_BROADWELL() instead of IS_GEN8() in forcewake code drm/i915: Don't call gen8_fbc_sw_flush() on chv ...
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ssh://people.freedesktop.org/~/linuxDave Airlie authored
Pull in first set of changes from Ben for ast on ppc. I've done a quick boot test on x86 and it still seems to boot. * 'drm-next-ast-fixes' of ssh://people.freedesktop.org/~/linux: drm/ast: Cleanup analog init code path drm/ast: Don't assume DVO enabled means SIL164 on uninitialized chips drm/ast: Properly initialize P2A base before using it in ast_init_3rdtx() drm/ast: POST chip at probe time if VGA not enabled drm/ast: Try to use MMIO registers when PIO isn't supported
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Y.C. Chen authored
Signed-off-by:
Egbert Eich <eich@suse.com> Tested-by:
Steven You2 Liang <liangyou2@lenovo.com> Signed-off-by:
Y.C. Chen <yc_chen@aspeedtech.com> v3: based on [PATCH 1/2] drm/ast: Add missing entry to dclk_table[]. Add reduced blanking modes, improve mode matching to identify these modes by thier sync polarities. [airlied: argh whitespace damage] Signed-off-by:
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Dave Airlie authored
This is requested to get the fixes for intel and radeon into the same tree for future development work. i915_display.c: fix missing dev_priv conflict.
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- 15 Sep, 2014 2 commits
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git://anongit.freedesktop.org/git/nouveau/linux-2.6Dave Airlie authored
This is the main merge request for Nouveau 3.18, overview: - various bits of roy's gt21x clock work - various bits of kepler memory clock work (don't get too excited, there's at least one more major bit left that's busting higher freqs) - misc fan control improvements - kepler hdmi infoframe fixes - dp audio - l2 cache + cbc improvements * 'linux-3.18' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (68 commits) drm/gt214-/disp: enable dp audio drm/gt214-/kms: fix hda eld regression drm/g94-/disp: calculate some dp audio constants drm/gt214-/kms: perform hda codec setup on displayport too drm/gk104-/disp: infoframe registers moved yet again on kepler drm/nouveau/bios: parse older ramcfg/timing data like we do newer ones drm/nva3/fb/ram: Per-partition regs drm/nouveau/fb/ram: Support strided regs drm/nv50/fb/ram: Store the number of partitions in the designated fields drm/nv50/kms: Set VBLANK time in modeset script drm/nouveau/bios: Add rammap support for version 1.0 drm/gf100-/pwr/memx: block host and fifo around reclock drm/nouveau/pwr/memx: fix command ordering around block/unblock drm/nouveau/pwr/memx: rename fb off/on to block/unblock drm/nva3/clk: Pause the GPU before reclocking drm/nouveau/gpio: rename g92 class to g94 drm/gk104-/fb/ram: move fb enable/disable to same place as nvidia drm/gk104/fb/ram: twiddle some more bits when reclocking drm/nouveau/bios: parse another large chunk of random memory config data drm/gk104-/fb/ram: perform certain steps only when bios data differs ...
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Ben Skeggs authored
Signed-off-by:Ben Skeggs <bskeggs@redhat.com>
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