- 04 Oct, 2007 19 commits
-
-
Scott Wood authored
The 8272 (and presumably other PCI PQ2 chips) appear to have the same issue as the 83xx regarding PCI streaming DMA. Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
-
Scott Wood authored
This provides a generic way for board code to set up CPM pins, rather than directly poking magic values into registers. Signed-off-by:
-
Scott Wood authored
Signed-off-by:
-
Scott Wood authored
Mostly sparse fixes (__iomem annotations, etc); also, cpm2_immr is used rather than creating many temporary mappings. Signed-off-by:
-
John Traill authored
The 8xx can only support a max of 8M during early boot (it seems a lot of 8xx boards only have 8M so the bug was never triggered), but the early allocator isn't aware of this. The following change makes it able to run with larger memory. Signed-off-by:
John Traill <john.traill@freescale.com> Signed-off-by:
Vitaly Bordug <vitb@kernel.crashing.org> Signed-off-by:
-
Scott Wood authored
The CPU15 erratum on MPC8xx chips can cause incorrect code execution under certain circumstances, where there is a conditional or indirect branch in the last word of a page, with a target in the last cache line of the next page. This patch implements one of the suggested workarounds, by forcing a TLB miss whenever execution crosses a page boundary. This is done by invalidating the pages before and after the one being loaded into the TLB in the ITLB miss handler. Signed-off-by:
-
Scott Wood authored
These let board code set up pins and clocks without having to put magic numbers directly into the registers. The clock function is mostly duplicated from the cpm2 version; hopefully this stuff can be merged at some point. Signed-off-by:
-
Scott Wood authored
1. Keep a global mpc8xx_immr mapping, rather than constantly creating temporary mappings. 2. Look for new fsl,cpm1 and fsl,cpm1-pic names. 3. Always reset the CPM when not using the udbg console; this is required in case the firmware initialized a device that is incompatible with one that the kernel is about to use. 4. Remove some superfluous casts and header includes. 5. Change a usage of IMAP_ADDR to get_immrbase(). 6. Use phys_addr_t, not uint, for dpram_pbase. 7. Various sparse-related fixes, such as __iomem annotations. 8. Remove mpc8xx_show_cpuinfo, which doesn't provide anything useful beyond the generic cpuinfo handler. 9. Move prototypes for 8xx support functions from board files to sysdev/commproc.h. Signed-off-by:
-
Scott Wood authored
1. Move CONSISTENT_START on 8xx so that it doesn't overlap the IMMR mapping. 2. The wrong register was being loaded into SPRN_MD_RPN. Signed-off-by:
-
Scott Wood authored
This prevents some bootloader/bootwrapper characters from being lost. Signed-off-by:
-
Scott Wood authored
Mostly a bunch of direct access to in/out conversions, plus a few cast removals, __iomem annotations, and miscellaneous cleanup. Signed-off-by:
-
Scott Wood authored
The existing OF glue code was crufty and broken. Rather than fix it, it has been removed, and the serial driver now talks to the device tree directly. The non-CONFIG_PPC_CPM_NEW_BINDING code can go away once CPM platforms are dropped from arch/ppc (which will hopefully be soon), and existing arch/powerpc boards that I wasn't able to test on for this patchset get converted (which should be even sooner). Signed-off-by:
-
Scott Wood authored
Signed-off-by:
-
Scott Wood authored
fsl_get_immr() uses /soc/ranges to determine the immr. mpc885_get_clock() transforms a crystal frequency into a system frequency according to the PLL register settings. pq2_get_clocks() does the same as the above for the PowerQUICC II, except that it produces several different clocks. The mpc8xx/pq2 set_clocks() functions modify common properties in the device tree based on the given clock data. The mpc885/pq2 fixup_clocks() functions call get_clocks(), and pass the results to set_clocks(). Signed-off-by:
David Gibson <david@gibson.dropbear.id.au> Signed-off-by:
-
Scott Wood authored
Consensus was reached to put PCI nodes at the root of the tree (and not under /soc), but the phandle to a control node was rejected in favor of simply not worrying about /pci/reg overlapping /soc/ranges. This updates cuboot-82xx to not look for the phandle. Signed-off-by:
-
Scott Wood authored
This code assumes that the ports have been previously set up, with buffers in DPRAM. Signed-off-by:
-
Scott Wood authored
This introduces a new device binding for the CPM and other devices on these boards. Some of the changes include: 1. Proper namespace scoping for Freescale compatibles and properties. 2. Use compatible rather than things like device_type and model to determine which particular variant of a device is present. 3. Give the drivers the relevant CPM command word directly, rather than requiring it to have a lookup table based on device-id, SCC v. SMC, and CPM version. 4. Specify the CPCR and the usable DPRAM region in the CPM's reg property. Boards that do not require the legacy bindings should select CONFIG_PPC_CPM_NEW_BINDING to enable the of_platform CPM devices. Once all existing boards are converted and tested, the config option can become default y to prevent new boards from using the old model. Once arch/ppc is gone, the config option can be removed altogether. Signed-off-by:
-
Scott Wood authored
As suggested by David Gibson, now that we have a separate node for the baud rate generators, it's better to use the standard clock-frequency property than a cpm-node-level fsl,brg-frequency property. This patch updates existing places where fsl,brg-frequency is used. Signed-off-by:
-
Paul Mackerras authored
Commit 8112753b made 44x in ARCH=powerpc builds use cpu setup routines in cpu_setup_44x.S, but didn't make a similar change for ARCH=ppc, and consequently the ARCH=ppc builds fail with undefined symbols (since both use the same cputable.c). This fixes it by including cpu_setup_44x.S in the ARCH=ppc builds, and by taking out the now-redundant FPU initialization in arch/ppc/kernel/head_44x.S. Signed-off-by:
Paul Mackerras <paulus@samba.org>
-
- 03 Oct, 2007 21 commits
-
-
Grant Likely authored
Reverts commit a15da8ef This driver is used by devices other than the xilinx opb-uartlite which depend on bytewise access to the registers. The change to 32 bit access does not work on these devices. Signed-off-by:
Grant Likely <grant.likely@secretlab.ca> Acked-by:
Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by:
Josh Boyer <jwboyer@linux.vnet.ibm.com>
-
Grant Likely authored
Add macros to define register names to improve readability. Signed-off-by:
-
Grant Likely authored
This simply adds the boilerplate default Ethernet address to embed_config for the Xilinx platform (bug fix). Signed-off-by:
-
Grant Likely authored
XilnixFB can be used by more than just arch/ppc. Move the data structure definition into include/linux/xilinxfb.h so it can be used by microblaze and arch/powerpc Signed-off-by:
-
Grant Likely authored
Flush the uartlite RX fifo so that characters typed before entry into the zImage wrapper do not muck up the kernel command line. Signed-off-by:
-
Josh Boyer authored
Tell git to ignore the generated treeImage.* files in arch/powerpc/boot Signed-off-by: -
Grant Likely authored
By configuring it earlier we get console output sooner which is helpful for debugging when the kernel crashes before the serial drivers are initialized. Signed-off-by:
-
Grant Likely authored
Add of_platform bus binding so this driver can be used with arch/powerpc Signed-off-by:
-
Grant Likely authored
Tidy the comments to split the driver into logical section; the main driver, the console driver, the platform bus binding, and module initialization and teardown. Signed-off-by:
-
Grant Likely authored
Separate the bus binding code from the driver structure allocation code in preparation for adding the of_platform_bus bindings needed by arch/powerpc Signed-off-by:
-
Grant Likely authored
Changed to make the following OF_platform bus binding patch a wee bit cleaner Signed-off-by:
-
Grant Likely authored
Changed to match naming convention used in the rest of the module Signed-off-by:
-
Grant Likely authored
The Uartlite data sheet defines the registers as 32 bit wide. This patch changes the register access to use 32 bit transfers and eliminates the magic +3 offset which is currently required to make the device work. Signed-off-by:
John Williams <jwilliams@itee.uq.edu.au> Signed-off-by:
-
Grant Likely authored
Signed-off-by:
-
Grant Likely authored
Adds support for generic Xilinx Virtex boards. Any board which specifies "xilinx,virtex" in the compatible property will make use of this board support. Signed-off-by:
-
Grant Likely authored
Adds support for the Xilinx opb-intc interrupt controller Signed-off-by:
-
Grant Likely authored
Add the needed kconfig macros to enable Xilinx Virtex board support Signed-off-by:
-
Grant Likely authored
Allows the bootwrapper to use the uartlite device for console output. Signed-off-by:
-
Valentine Barshak authored
Add a workaround for PowerPC 440EPx/GRx incorrect write to DDR SDRAM errata. Data can be written to wrong address in SDRAM when write pipelining enabled on plb0. We disable it in the cpu_setup for these processors at early init. Signed-off-by:
Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by:
-
Valentine Barshak authored
The PowerPC 440EP(x) FPU init is currently done in head_44x under ifdefs. Since we should support more then one board in the same kernel, we move FPU initialization code from head_44x to cpu_setup_44x and add cpu_setup callbacks for 440EP(x). Signed-off-by:
-
Valentine Barshak authored
This adds cpu_setup functionality for ppc44x platform. Low level cpu-spefic initialization routines should be placed in cpu_setup_44x.S and a callback should be added to cputable. The cpu_setup is invoked by identify_cpu() function at early init. Signed-off-by:
-
