- 20 May, 2021 39 commits
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Hugo Hu authored
Previous patch caused crash and had been reverted. This patch addresses the issue without regression. [Why] 1. Driver use umachannelnumber to calculate watermarks for stutter. In asymmetric memory config, the actual bandwidth is less than dual-channel. The bandwidth should be the same as single-channel. 2. We found single rank dimm need additional delay time for stutter. [How] Get information from each DIMM. Treat memory config as a single-channel for asymmetric memory in bandwidth calculating. Add additional delay time for single rank dimm. Signed-off-by:
Hugo Hu <hugo.hu@amd.com> Reviewed-by:
Sung Lee <Sung.Lee@amd.com> Acked-by:
Stylon Wang <stylon.wang@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Lijo Lazar authored
When determinism mode is disabled on aldebaran, max GFX clock will be reset to default max frequency value. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
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Lijo Lazar authored
v1: Use the current and custom pstate frequencies to track the current and user-set min/max values in manual and determinism mode. Previously, only actual_* value was used to track the currrent and user requested value. The value will get reassigned whenever user requests a new value with pp_od_clk_voltage node. Hence it will show incorrect values when user requests an invalid value or tries a partial request without committing the values. Separating out to custom and current variable fixes such issues. v2: Remove redundant if-else check Signed-off-by:
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Lijo Lazar authored
Add custom member for user requested custom frequency, level mask or min/max frequencies. Add curr member to keep track of the current active values. Signed-off-by:
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John Clements authored
Only clear RAS error counters if perestent EDC harvesting is not supported Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Changfeng authored
There is problem with 3DCGCG firmware and it will cause compute test hang on picasso/raven1. It needs to disable 3DCGCG in driver to avoid compute hang. Signed-off-by:
Changfeng <Changfeng.Zhu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Peng Ju Zhou authored
there are 2 hubs to flush in the gmc, to make it easier to debug when hub flush failed, refine the logs. Signed-off-by:
Peng Ju Zhou <PengJu.Zhou@amd.com> Reviewed-by:
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Peng Ju Zhou authored
KMD should not the program these registers, so skip them in the SRIOV environment. Signed-off-by:
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Yi Li authored
When PAGE_SIZE is larger than AMDGPU_PAGE_SIZE, the number of GPU TLB entries which need to update in amdgpu_map_buffer() should be multiplied by AMDGPU_GPU_PAGES_IN_CPU_PAGE (PAGE_SIZE / AMDGPU_PAGE_SIZE). Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Yi Li <liyi@loongson.cn> Signed-off-by:
Huacai Chen <chenhuacai@loongson.cn> Signed-off-by:
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Philip Yang authored
Need do a heavy-weight TLB flush to make sure we have no more dirty data in the cache for the unmapped pages. Define enum TLB_FLUSH_TYPE, add flush_type parameter to amdgpu_amdkfd_flush_gpu_tlb_pasid. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
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Philip Yang authored
This reverts commit 1704ac8e. After "drm/amdgpu: flush TLB if valid PDE turns into PTE" is checked in, this workaround is not needed. Signed-off-by:
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Jiawei Gu authored
Initialize unique_id from PF2VF under virtualization. V2: skip smu_get_unique_id() under virtualization Signed-off-by:
Jiawei Gu <Jiawei.Gu@amd.com> Acked-by:
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Philip Yang authored
Mapping huge page, 2MB aligned address with 2MB size, uses PDE0 as PTE. If previously valid PDE0, PDE0.V=1 and PDE0.P=0 turns into PTE, this requires TLB flush, otherwise page table walker will not read updated PDE0. Change page table update mapping to return table_freed flag to indicate the previously valid PDE may have turned into a PTE if page table is freed. Signed-off-by:
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Christian König authored
Imported BOs don't have a pagelist any more. Signed-off-by:
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Christian König authored
Not used outside of that file. Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Signed-off-by:
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Christian König authored
Drop the last user of drm_mm_node. Signed-off-by:
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Christian König authored
This avoids reallocating scanout BOs on first pin in a lot of cases. Signed-off-by:
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Christian König authored
One of the last remaining uses of drm_mm_node. Signed-off-by:
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Christian König authored
Now that we found the underlying problem we can re-apply this patch. This reverts commit 6b44b667. v2: rebase on KFD changes Signed-off-by:
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Hawking Zhang authored
Only send boot_config cmd to ASICs that support dynamic boot config. Otherwise, the boot_config cmd will fail. Signed-off-by:
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Hawking Zhang authored
Check firmware flags to determine whether dynmaic boot config is supported or not. Signed-off-by:
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Hawking Zhang authored
Check cached firmware_flags to determin whether two stage mem training is supported or not. Signed-off-by:
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Hawking Zhang authored
Check cached firmware_flags to determine whether sram ecc is supported or not. Signed-off-by:
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Hawking Zhang authored
Check cached firmware_flags to determine if gpu virtualization is supported in vbios Signed-off-by:
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Hawking Zhang authored
Fimware capability was changed from 16 bits to 32 bits for atomfirmware. add helper funciton to query firmware capability and cache the value at early stage. Signed-off-by:
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Bokun Zhang authored
- Update SRIOV PF2VF header with latest revision - Extend existing function in amdgpu_virt.c to read MM bandwidth config from PF2VF message - Add SRIOV Sienna Cichlid codec array and update the bandwidth with PF2VF message v2: squash in removal of unused variable (Alex) Signed-off-by:
Bokun Zhang <bokun.zhang@amd.com> Reviewed-by:
Monk liu <monk.liu@amd.com> Reviewed-by:
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Felix Kuehling authored
MTYPE UC was used for a specific use case that ended up not being implemented. Use NC for better performance for coarse-grained memory where cache coherence during shader execution is not required. Signed-off-by:
Oak Zeng <Oak.Zeng@amd.com> Signed-off-by:
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Felix Kuehling authored
MTYPE UC was used for a specific use case that ended up not being implemented. Use NC for better performance for coarse-grained memory where cache coherence during shader execution is not required. Signed-off-by:
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Jinzhou Su authored
Add compile flag CONFIG_DEBUG_FS to clear the warning: unused variable 'amdgpu_securedisplay_debugfs_ops' Signed-off-by:
Jinzhou Su <Jinzhou.Su@amd.com> Acked-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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Dennis Li authored
The user applications maybe register the KFD_EVENT_TYPE_HW_EXCEPTION and KFD_EVENT_TYPE_MEMORY events, driver could notify them when poison data consumed. Beside that, some applications maybe register SIGBUS signal hander. These applications will handle poison data by themselves, exit or re-create context to re-dispatch works. Signed-off-by:
Dennis Li <Dennis.Li@amd.com> Reviewed-by:
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Kai-Heng Feng authored
Screen flickers rapidly when two 4K 60Hz monitors are in use. This issue doesn't happen when one monitor is 4K 60Hz (pixelclock 594MHz) and another one is 4K 30Hz (pixelclock 297MHz). The issue is gone after setting "power_dpm_force_performance_level" to "high". Following the indication, we found that the issue occurs when sclk is too low. So resolve the issue by disabling sclk switching when there are two monitors requires high pixelclock (> 297MHz). v2: - Only apply the fix to Oland. Signed-off-by:
Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by:
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Philip Yang authored
If xnack is on, new range is created to recover retry vm fault or created by SVM API calls, set all GPUs have access to the range. Signed-off-by:
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Lijo Lazar authored
Update aldebaran driver-PMFW interface to version 0x07 Signed-off-by:
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Roy Sun authored
Move the process of cancelling hrtimer to sw_fini Signed-off-by:
Roy Sun <Roy.Sun@amd.com> Reviewed-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
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Kenneth Feng authored
Since ASPM function has been stable, we don't need to add the modprobe parameter and we can enable ASPM by default. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by:
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Likun Gao authored
Update the method of disabling VCN IP for specific SKU for navi1x ASIC, it will judge whether should add the related IP at the function of amdgpu_device_ip_block_add(). Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Likun GAO authored
Judgement whether to add an sw ip according to the harvest info. v2: fix indentation (Alex) Signed-off-by:
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Dennis Li authored
It is possible that the previous waves have exited before others are created, so the other waves maybe reuse pyhsical resouces left by previous ones. Therefore add barrier instruction to synchronize waves within the same threadgroup. Signed-off-by:
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Alex Deucher authored
Add missing structure elements. Fixes: 0dd79532 ("drm/amdgpu/display: Implement functions to let DC allocate GPU memory") Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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- 12 May, 2021 1 commit
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Alex Deucher authored
Fixes: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c: In function ‘amdgpu_dm_initialize_drm_device’: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3726:7: error: implicit declaration of function ‘register_outbox_irq_handlers’; did you mean ‘register_hpd_handlers’? [-Werror=implicit-function-declaration] 3726 | if (register_outbox_irq_handlers(dm->adev)) { | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ | register_hpd_handlers Fixes: 81927e28 ("drm/amd/display: Support for DMUB AUX") Reviewed-by:Jude Shih <shenshih@amd.com> Signed-off-by:
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