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    • Matt Roper's avatar
      drm/i915/pvc: Add register steering · e0d7371b
      Matt Roper authored
      Ponte Vecchio no longer has MSLICE or LNCF steering, but the bspec does
      document several new types of multicast register ranges.  Fortunately,
      most of the different MCR types all provide valid values at instance
      (0,0) so there's no need to read fuse registers and calculate a
      non-terminated instance.  We'll lump all of those range types (BSLICE,
      HALFBSLICE, TILEPSMI, CC, and L3BANK) into a single category called
      "INSTANCE0" to keep things simple.  We'll also perform explicit steering
      for each of these multicast register types, even if the implicit
      steering setup for COMPUTE/DSS ranges would have worked too; this is
      based on guidance from our hardware architects who suggested that we
      move away from implicit steering and start explicitly steer all MCR
      register accesses on modern platforms (we'll work on transitioning
      COMPUTE/DSS to explicit steering in the future).
      
      Note that there's one additional MCR range type defined in the bspec
      (SQIDI) that we don't handle here.  Those ranges use a different
      steering control register that we never touch; since instance 0 is also
      always a valid setting there, we can just ignore those ranges.
      
      Finally, we'll rename the HAS_MSLICES() macro to HAS_MSLICE_STEERING().
      PVC hardware still has units referred to as mslices, but there's no
      register steering based on mslice for this platform.
      
      v2:
       - Rebase on other recent changes
       - Swap two table rows to keep table sorted & easy to read.  (Harish)
      
      Bspec: 67609
      Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
      Reviewed-by: default avatarHarish Chegondi <harish.chegondi@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20220608170700.4026648-1-matthew.d.roper@intel.com
      e0d7371b
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