- 11 Dec, 2023 21 commits
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Yang Yingliang authored
Change legacy name master/slave to modern name host/target or controller. No functional changed. Signed-off-by:
Yang Yingliang <yangyingliang@huawei.com> Link: https://msgid.link/r/20231128093031.3707034-22-yangyingliang@huawei.comSigned-off-by:
Mark Brown <broonie@kernel.org>
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Yang Yingliang authored
Change legacy name master/slave to modern name host/target or controller. No functional changed. Signed-off-by:
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Yang Yingliang authored
Change legacy name master to modern name host or controller. No functional changed. Signed-off-by:
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Yang Yingliang authored
Change legacy name master to modern name host or controller. No functional changed. Signed-off-by:
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Yang Yingliang authored
Change legacy name master to modern name host or controller. No functional changed. Signed-off-by:
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Yang Yingliang authored
Switch to use modern name function devm_spi_alloc_host(). No functional changed. Signed-off-by:
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Yang Yingliang authored
Change legacy name master to modern name host or controller. No functional changed. Signed-off-by:
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Yang Yingliang authored
Change legacy name master to modern name host or controller. No functional changed. Signed-off-by:
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Yang Yingliang authored
Change legacy name master/slave to modern name host/target or controller. No functional changed. Signed-off-by:
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Yang Yingliang authored
Change legacy name master to modern name host or controller. No functional changed. Signed-off-by:
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Yang Yingliang authored
Change legacy name master/slave to modern name host/target or controller. No functional changed. Signed-off-by:
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Yang Yingliang authored
Change legacy name master/slave to modern name host/target or controller. No functional changed. Signed-off-by:
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Yang Yingliang authored
Change legacy name master to modern name host or controller. No functional changed. Signed-off-by:
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Yang Yingliang authored
Change legacy name master/slave to modern name host/target or controller. No functional changed. Signed-off-by:
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Yang Yingliang authored
Change legacy name master to modern name host or controller. No functional changed. Signed-off-by:
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Yang Yingliang authored
Change legacy name master to modern name host or controller. No functional changed. Signed-off-by:
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Yang Yingliang authored
Change legacy name master/slave to modern name host/target. No functional changed. Signed-off-by:
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Yang Yingliang authored
Change legacy name master to modern name host or controller. No functional changed. Signed-off-by:
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Yang Yingliang authored
Change legacy name master/slave to modern name host/target or controller. No functional changed. Signed-off-by:
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Yang Yingliang authored
Change legacy name master to modern name host or controller. No functional changed. Signed-off-by:
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Yang Yingliang authored
Switch to use modern name function spi_alloc_host(). No functional changed. Signed-off-by:
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- 09 Dec, 2023 1 commit
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Mark Brown authored
Merge series from Andy Shevchenko <andriy.shevchenko@linux.intel.com>: A couple of documentation updates.
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- 08 Dec, 2023 3 commits
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Randy Dunlap authored
Since linux/of_platform.h had included linux/platform_device.h and since that inclusion was removed, this driver now needs to include the latter header file explicitly to prevent build errors: drivers/spi/spi-mpc52xx.c: In function 'mpc52xx_spi_probe': drivers/spi/spi-mpc52xx.c:396:20: error: invalid use of undefined type 'struct platform_device' and more like that. Fixes: 0d18bcdebb2f ("of: Stop circularly including of_device.h and of_platform.h") Signed-off-by:Randy Dunlap <rdunlap@infradead.org> Cc: Rob Herring <robh@kernel.org> Cc: Mark Brown <broonie@kernel.org> Cc: linux-spi@vger.kernel.org Link: https://lore.kernel.org/r/20231208185927.14124-1-rdunlap@infradead.orgSigned-off-by:
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Andy Shevchenko authored
Update DMA mapping and using logic in the documentation to follow what the code does. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231208170436.3309648-3-andriy.shevchenko@linux.intel.comSigned-off-by:
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Andy Shevchenko authored
Replace master/slave by host/peripheral language in the documentation. Signed-off-by:
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- 07 Dec, 2023 4 commits
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Mark Brown authored
Merge series from Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>: This patch series adds support to the SPI framework for using multiple chip selects.
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Amit Kumar Mahapatra authored
AMD-Xilinx GQSPI controller has two advanced mode that allows the controller to consider two flashes as one single device. One of these two mode is the parallel mode in which each byte of data is stored in both devices, the even bits in the lower flash & the odd bits in the upper flash. The byte split is automatically handled by the QSPI controller. The other mode is the stacked mode in which both the flashes share the same SPI bus but each of the device contain half of the data. In this mode, the controller does not follow CS requests but instead internally wires the two CS levels with the value of the most significant address bit. For supporting both these modes SPI core need to be updated for providing multiple CS for a single SPI device. For adding multi CS support the SPI device need to be aware of all the CS values. So, the "chip_select" member in the spi_device structure is now an array that holds all the CS values. spi_device structure now has a "cs_index_mask" member. This acts as an index to the chip_select array. If nth bit of spi->cs_index_mask is set then the driver would assert spi->chip_select[n]. In parallel mode all the chip selects are asserted/de-asserted simultaneously and each byte of data is stored in both devices, the even bits in one, the odd bits in the other. The split is automatically handled by the GQSPI controller. The GQSPI controller supports a maximum of two flashes connected in parallel mode. A SPI_CONTROLLER_MULTI_CS flag bit is added in the spi controller flags, through ctlr->flags the spi core will make sure that the controller is capable of handling multiple chip selects at once. For supporting multiple CS via GPIO the cs_gpiod member of the spi_device structure is now an array that holds the gpio descriptor for each chipselect. CS GPIO is not tested on our hardware, but it has been tested by @Stefan https://lore.kernel.org/all/005001da1efc$619ad5a0$24d080e0$@opensource.cirrus.com/Signed-off-by:
Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Tested-by:
Stefan Binding <sbinding@opensource.cirrus.com> Link: https://lore.kernel.org/r/20231125092137.2948-4-amit.kumar-mahapatra@amd.comSigned-off-by:
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Amit Kumar Mahapatra authored
In preparation for adding multiple CS support for a device, set/get functions were introduces accessing spi->chip_select in 'commit 303feb3c ("spi: Add APIs in spi core to set/get spi->chip_select and spi->cs_gpiod")'. Replace spi->chip_select with spi_get_chipselect() API. Signed-off-by:
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Amit Kumar Mahapatra authored
In preparation for adding multiple CS support for a device, set/get functions were introduces accessing spi->chip_select in 'commit 303feb3c ("spi: Add APIs in spi core to set/get spi->chip_select and spi->cs_gpiod")'. Replace spi->chip_select with spi_get_chipselect() API. Signed-off-by:
Lee Jones <lee@kernel.org>
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- 06 Dec, 2023 10 commits
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Mark Brown authored
Merge series from David Lechner <dlechner@baylibre.com>: We are working towards adding support for the offload feature [1] of the AXI SPI Engine IP core. Before we can do that, we want to make some general fixes and improvements to the driver. In order to avoid a giant series with 35+ patches, we are splitting this up into a few smaller series. This is a continuation of the work started in [2] which has been applied to spi/for-6.8 [3]. This series must be applied on top of that series to apply cleanly. Once this series is applied, we will follow up with the 3rd series that implements the offload support. The offload support will also involve the IIO subsystem (a new IIO driver will depend on the new SPI offload feature), so I'm mentioning this now in case we want to do anything ahead of time to prepare for that (e.g. putting all of these changes on a separate branch). [1]: https://wiki.analog.com/resources/fpga/peripherals/spi_engine/offload [2]: https://lore.kernel.org/linux-spi/20231117-axi-spi-engine-series-1-v1-0-cc59db999b87@baylibre.com/ [3]: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git/log/?h=for-6.8
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David Lechner authored
If there is an issue with the AXI SPI Engine hardware a scheduled transfer might never be completed and spi_sync() will block forever. This due to the uninterruptible wait for completion waiting for the spi_finalize_current_message() that never comes. Add a watchdog timer that will abort a transfer 5 seconds after it has been started. This will potentially leave the hardware in a broken state but it allows software to recover and allow to better diagnose the underlying issue. Co-developed-by:
Lars-Peter Clausen <lars@metafoo.de> Signed-off-by:
David Lechner <dlechner@baylibre.com> Acked-by:
Michael Hennerich <michael.hennerich@analog.com> Acked-by:
Nuno Sa <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20231204-axi-spi-engine-series-2-v1-9-063672323fce@baylibre.comSigned-off-by:
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David Lechner authored
Now that the AXI SPI Engine driver has support for the various CS delays requested through struct spi_message, we don't need to add a separate delay to the CS assertion instruction. Otherwise, we end up with longer than requested delays. Signed-off-by:
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David Lechner authored
This modifies the ADI AXI SPI Engine driver to restore the clkdiv configuration register at the end of a SPI message. Having the clkdiv in a known state is needed to be able to add a new command in the future that only performs a delay without any SPI transfers. Furthermore having that state be the smallest possible divider will allow these delays to have the highest possible precision. Changing the initial value of clk_div from -1 to 1 is now possible because we know the function will always be called with a known clkdiv config register state. Making this change will also have the effect of not emitting a clkdiv configuration register instruction in cases where the maximum sclk rate is used. Having one less instruction to process reduces delays on the bus which will be beneficial when we implement offload support to enable reading data from devices at very high rates. Signed-off-by:
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David Lechner authored
This adds handling of xfer->cs_change_delay to the AXI SPI Engine driver. Signed-off-by:
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David Lechner authored
This replaces the xfer parameter of spi_engine_gen_sleep() in the AXI SPI Engine driver with parameters for the delay in nanoseconds and the SPI SCLK rate. This will allow this function to be used by callers in the future that do not have a spi_transfer struct. Signed-off-by:
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David Lechner authored
This fixes the sleep ticks calculation when generating sleep instructions in the AXI SPI Engine driver. The previous calculation was ignoring delays less than one microsecond and missed a microsecond to second conversion factor. This fixes the first issue by not rounding to microseconds. Now that xfer->effective_speed_hz is guaranteed to be set correctly, we can use that to simplify the calculation. This new calculation replaces the old incorrect math. Also add unit suffix to the delay variable for clarity while we are touching this. Signed-off-by:
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David Lechner authored
Now that host->max_speed_hz and xfer->effective_speed_hz are properly set, we can use them instead of having to do more complex calculations to get the clock divider for each transfer. This removes the spi_engine_get_clk_div() function and replaces it with just dividing the two clock rates. Since the hardware register value is the divider minus one, we need to subtract one. Subtracting one was previously done in the spi_engine_get_clk_div() function. Signed-off-by:
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David Lechner authored
This adds a new spi_engine_precompile_message() function to the ADI AXI SPI Engine driver to populate the xfer->effective_speed_hz field since the SPI core doesn't/can't do this for us. This driver is already using spi_delay_to_ns() which depends on effective_speed_hz to get an accurate value in some cases. Having an effective_speed_hz value can also be used in future changes to simplify other code. Signed-off-by:
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David Lechner authored
In the AXI SPI Engine driver, the spi_engine_compile_message() function does not return any error and none of the callers check the return value. So we can change the return type to void and drop the return 0. Signed-off-by:
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- 04 Dec, 2023 1 commit
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Yang Yingliang authored
cqspi_jh7110_clk_init() is called after clk_prepare_enable(cqspi->clk), if it fails, it should goto label 'probe_reset_failed' to disable cqspi->clk. In the error path after calling cqspi_jh7110_clk_init(), cqspi_jh7110_disable_clk() need be called. Fixes: 33f1ef6d ("spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI") Signed-off-by:
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