- 09 Jun, 2023 40 commits
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Jonathan Kim authored
If a CPU and GPU are xGMI connected but the GPU is hiveless with respect to other GPUs, create a new CPU-GPU hive using the GPU's PCI device location ID as the new hive ID to maintain fine grain memory access usage. Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Philip Yang authored
kfd node allocation outside kfd->num_nodes loop is not needed and causes memory leak because kfd->num_nodes is at least equal to 1. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
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Rajneesh Bhardwaj authored
This allows backing ttm_tt structure with pages from different NUMA pools. Tested-by:
Graham Sider <graham.sider@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by:
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Lijo Lazar authored
For MQD init, an XCC's queue is selected with GRBM select. However, for initialization of MQD, values read from logical XCC0 registers are used. This results in garbage values being read from XCC0 whose queue is not selected. Change to read from the right XCC for MQD initialization. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Harish Kasiviswanathan authored
‘for’ loop initial declarations are only allowed in C99 or C11 mode Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by:
Mukul Joshi <mukul.joshi@amd.com> Signed-off-by:
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Lijo Lazar authored
Enable coarse grain clockgating/light sleep for GC v9.4.3. Remove programming that is not meant for GC 9.4.3. Signed-off-by:
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Lijo Lazar authored
Program different ranges in each XCC with MEC_DOORBELL_RANGE_LOWER/HIGHER. Keeping the same range causes CPF in other XCCs also to be busy when an IB packet is submitted to KCQ. Only the XCC which processes the packet comes back to idle afterwards and this causes other CPs not be idle. This in turn affects clockgating behavior as RLC doesn't get idle interrupt. LOWER/HIGHER covers only KIQ/KCQs which are per XCC queues. Assigning different ranges doesn't seem to have any side effect as user queue ranges are outside of this range. User queue tests - PM4 through KFD and AQL through rocr - have the same results after this change. Signed-off-by:
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Lijo Lazar authored
During ASIC wide reset, SDMA shouldn't be clockgated and be ready to accept freeze requests from PMFW. For that, don't stop SDMA engine during reset and keep the clocks active. Signed-off-by:
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Rajneesh Bhardwaj authored
GFXIP 9.4.3 could be in APU or carveout mode but we cannot use the xgmi.connected_to_cpu flag to identify the iolinks type. Use appropriate APU or Carveout mode based condition to report xgmi connection in kfd topology. Reviewed-by:
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James Zhu authored
Add num_xcps return. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
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James Zhu authored
[WA] Increase AMDGPU_MAX_HWIP_RINGS to 64 to support more compute ring resource. Later need redesign with queue/prirority/scheduler factors to reduce AMDGPU_MAX_HWIP_RINGS. Signed-off-by:
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James Zhu authored
Signed-off-by:
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Lijo Lazar authored
Certain instances of VCN/JPEG IPs may not be usable. Fetch the information from harvest table. Signed-off-by:
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Graham Sider authored
Revert temporary dGPU VRAM MTYPE setting and align with expected coherency protocol. Signed-off-by:
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Asad kamal authored
SDMA v4.4.2 doesn't need explicit power gating control through PMFW Signed-off-by:
Asad kamal <asad.kamal@amd.com> Reviewed-by:
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James Zhu authored
Enable vcn/jpeg on vcn_v4_0_3. Signed-off-by:
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James Zhu authored
Enable indirect_sram mode on vcn_v4_0_3. Signed-off-by:
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James Zhu authored
Add unified queue support on vcn_v4_0_3. Signed-off-by:
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James Zhu authored
Add fwlog support on vcn_v4_0_3. Signed-off-by:
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James Zhu authored
vcn_v4_0_3 increased jpeg instances, need increasing MAX resources setting accordlingly. Signed-off-by:
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Lijo Lazar authored
Get information about active XCC and SDMAs from discovery table. Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
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Lijo Lazar authored
When overridden with module param, directly read discovery info from discovery binary instead of reading from VRAM. Signed-off-by:
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Felix Kuehling authored
Some AMD APUs may not have a dedicated VRAM. On such platforms the GART table should be allocated on the system memory. When real vram size is zero, place the GART table in system memory and create an SG BO to make it GPU accessible. v2: fix includes Reviewed-by:
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Lijo Lazar authored
Add logic for fine grain clock gating logic for GFX v9.4.3. The feature will be controlled using CG flags. Also, make a change so that RLC safe mode entry/exit is done only once during CG update sequence. Signed-off-by:
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Rajneesh Bhardwaj authored
On AMD APP APUs, to make UTCL2 snoop CPU caches, its not sufficient to rely on xgmi connected flag so add the logic to use is_app_apu to program the PDE_REQUEST_PHYSICAL bit correctly for gfxhub and mmhub both. Reviewed-by:
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Amber Lin authored
For GFX v9_4_3, set MTYPE_UC for memory access over PCIe. v4 - add missing indentation pointed out by Felix and add his reviewed-by tag. v3 - add missing logic for the svm path. v2 - add amdgpu_xgmi_same_hive to separate access over xgmi from pcie Reviewed-by:
Amber Lin <Amber.Lin@amd.com> Signed-off-by:
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Lijo Lazar authored
Each compute cluster gets 8 compute queues in GFX v9.4.3. Fix the EOP buffer allocation so that compute queue on every XCC gets a unique address. Signed-off-by:
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Lijo Lazar authored
ASICs with GFX 9.4.3 support 48-bit addressing. Signed-off-by:
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Lijo Lazar authored
Use the right register for semaphore release during invalidation. Signed-off-by:
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Mukul Joshi authored
Setup rolling current_logical_xcc_id in MQD for GFX9.4.3 to ensure each queue starts at a different place and prevent hotspotting issues. Also, remove updating current_logical_xcc_id during queue update. Suggested-by:
Joseph Greathouse <Joseph.Greathouse@amd.com> Signed-off-by:
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Lijo Lazar authored
There is no need to check return value, as the function internally used - amdgpu_discovery_read_binary_from_vram() - returns void. Signed-off-by:
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Le Ma authored
The AMDGPU_GFXHUB was bind to each xcc in the logical order. Thus convert the node_id to logical xcc_id to index the correct AMDGPU_GFXHUB. And "node_id / 4" can get the correct AMDGPU_MMHUB0 index. Signed-off-by:
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Mukul Joshi authored
In GFX 9.4.3, there can be more than 8 SDMA engines. As a result, extended_engine_sel and engine_sel fields in MAP_QUEUES packet need to be updated to allow correct mapping of SDMA queues to these SDMA engines. Signed-off-by:
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Rajneesh Bhardwaj authored
Apply the GFXIP 9.4.3 specific snoop and mtype settings for various scenarios such as APU, APU in Carveout mode and dGPU mode. Note: This is expected to change due to: 1 - NPS > 1 support in future 2 - Hardware bugs found during initial asic bringup. Cc: Graham Sider <graham.sider@amd.com> Cc: Hawking Zhang <hawking.zhang@amd.com> Signed-off-by:
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Lijo Lazar authored
Use a mask of available active clusters instead of using only the number of active clusters. Signed-off-by:
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Lijo Lazar authored
SDMA instances per active cluster and SDMA instance mask are used to find the number of active clusters. Signed-off-by:
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Lijo Lazar authored
Move soc specific configuration details to aqua vanjaram specific file. Signed-off-by:
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Shiwu Zhang authored
Just like the KIQ, KCQ need to clear the doorbell related regs as well to avoid hangs when to load driver again after unloading. Signed-off-by:
Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by:
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Lijo Lazar authored
On ASICs with PSPv13.0.6, TMR is reserved at boot time. There is no need to allocate TMR region by driver. However, it's still required to send SETUP_TMR command to PSP. Signed-off-by:
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Lijo Lazar authored
Initialize with the IP specific functions needed for GFXHUB, GFX and SDMA. Signed-off-by:
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