- 04 Jun, 2015 36 commits
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Alex Deucher authored
Acked-by:
Christian König <christian.koenig@amd.com> Acked-by:
Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This adds the non-asic specific core driver code. v2: remove extra kconfig option v3: implement minor fixes from Fengguang Wu v4: fix cast in amdgpu_ucode.c Acked-by:
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Alex Deucher authored
This is the main header file for amdgpu. v2: remove stable comments Acked-by:
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Alex Deucher authored
This header defines asic families and attributes. Acked-by:
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Alex Deucher authored
This header provides the smc message interface for the driver. Acked-by:
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Alex Deucher authored
This header provides for format for the GCA blocks clear state (i.e., default state). Each GCA version has a specific clear state. Acked-by:
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Alex Deucher authored
These headers define the atombios table structure and driver interface. Acked-by:
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Alex Deucher authored
This header defines the ioctl interface to the driver. v2: remove stale tiling defines v3: add appropriate padding v4: remove executable bits on header Acked-by:
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Alex Deucher authored
These are register headers for the VCE (Video Codec Engine) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the VCE (Video Codec Engine) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the UVD (Universal Video Decoder) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the UVD (Universal Video Decoder) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the UVD (Universal Video Decoder) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the SMU (System Management Unit) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the SMU (System Management Unit) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the SMU (System Management Unit) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the SMU (System Management Unit) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the SMU (System Management Unit) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the SMU (System Management Unit) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the OSS (OS Services) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the OSS (OS Services) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the OSS (OS Services) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the OSS (OS Services) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the GMC (Graphics Memory Controller) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the GMC (Graphics Memory Controller) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the GMC (Graphics Memory Controller) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the GMC (Graphics Memory Controller) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the GCA (Graphics and Compute Array) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the GCA (Graphics and Compute Array) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the GCA (Graphics and Compute Array) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the DCE (Display and Composition Engine) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the DCE (Display and Composition Engine) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the DCE (Display and Composition Engine) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the BIF (Bus InterFace) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the BIF (Bus InterFace) block on the GPU. Acked-by:
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Alex Deucher authored
These are register headers for the BIF (Bus InterFace) block on the GPU. Acked-by:
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- 03 Jun, 2015 4 commits
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git://git.kraxel.org/linuxDave Airlie authored
Yay, thanks to Gerd for pull this together. * 'virtio-gpu-drm-next' of git://git.kraxel.org/linux: Add MAINTAINERS entry for virtio-gpu. Add virtio gpu driver. drm_vblank_get: don't WARN_ON in case vblanks are not initialized break kconfig dependency loop
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https://github.com/jsarha/linuxDave Airlie authored
Please pull the contents of "Use DRM component API in tilcdc to connect to tda998x" patch series. * 'linux-4.1.0-rc5-tilcdc-refactor' of https://github.com/jsarha/linux: drm/tilcdc: Force building of DRM_TILCDC_SLAVE_COMPAT drm/tilcdc: Add DRM_TILCDC_SLAVE_COMPAT for ti,tilcdc,slave binding support drm/tilcdc: use pm_runtime_irq_safe() drm/tilcdc: Add support for external tda998x encoder drm/tilcdc: Remove tilcdc slave support for tda998x driver drm/tilcdc: Fix module unloading
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Dave Airlie authored
Linux 4.1-rc6 backmerge 4.1-rc6 as some of the later pull reqs are based on newer bases and I'd prefer to do the fixup myself.
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Maarten Lankhorst authored
This fixes some regressions in i915 when converting to atomic. set_config failed with -EINVAL, and I received the following warning in dmesg: [drm:drm_atomic_crtc_check] [CRTC:20] active without enabled Solve this by clearing active when a crtc is disabled. Because crtc_state->enable implies that connectors are active the change from disabled->enabled can only happen for the crtc that's being set_config'd, and checking for !crtc_state->enable is sufficient here. Cc: dri-devel@lists.freedesktop.org Reviewed-by:
Rob Clark <robdclark@gmail.com> Signed-off-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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