- 04 Oct, 2016 40 commits
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James Hogan authored
When reading the CP0_EBase register containing the WG (write gate) bit, the ebase variable should be set to the full value of the register, i.e. on a 64-bit kernel the full 64-bit width of the register via read_cp0_ebase_64(), and on a 32-bit kernel the full 32-bit width including bits 31:30 which may be writeable. Signed-off-by:
James Hogan <james.hogan@imgtec.com> Signed-off-by:
Matt Redfearn <matt.redfearn@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14148/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Matt Redfearn authored
This patch enables the MIPS CPS driver for MIPSr6 CPUs. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Reviewed-by:
Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: linux-mips@linux-mips.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14228/Signed-off-by:
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Matt Redfearn authored
All calls to mips_cpc_lock_other should be wrapped in mips_cm_lock_other. This only matters if the system has CM3 and is using cpu idle, since otherwise a) the CPC lock is sufficent for CM < 3 and b) any systems with CM > 3 have not been able to use cpu idle until now. Signed-off-by:
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Matt Redfearn authored
MIPS CM3 changed the management of coherence. Instead of a coherence control register with a bitmask of coherent domains, CM3 simply has a coherence enable register with a single bit to enable coherence of the local core. Support this by clearing and setting this single bit to disable / enable coherence. Signed-off-by:
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Matt Redfearn authored
This patch adds support for CPUs implementing the MIPSr6 ISA to the CPS power management code. Three changes are necessary: 1. In MIPSr6, coupled coherence is necessary when CPUS implement multiple Virtual Processors (VPs). 2. MIPSr6 virtual processors are more like real cores and cannot yield to other VPs on the same core, so drop the MT ASE yield instruction. 3. To halt a MIPSr6 VP, the CPC VP_STOP register is used rather than the MT ASE TCHalt CP0 register. Signed-off-by:
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Matt Redfearn authored
Instead of selecting an implementation or vendor specific sync type for the required sync operations, always use the architecturally mandated sync types which previous patches have put in place. The selection of special sync types is now redundant an can be removed. Signed-off-by:
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Matt Redfearn authored
SYNC type 0 is defined in the MIPS architecture as a completion barrier where all loads/stores in the pipeline before the sync instruction must complete before any loads/stores subsequent to the sync instruction. In places where we require loads / stores be globally completed, use the standard completion sync stype. Signed-off-by:
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Matt Redfearn authored
Since R2 of the MIPS architecture, SYNC(0x10) has been an optional but architecturally defined ordering barrier. If a CPU does not implement it, the arch specifies that it must fall back to SYNC(0). In places where we require that the instruction stream not be reordered, but do not require that loads / stores are gloablly completed, use the defined standard sync stype. Signed-off-by:
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Matt Redfearn authored
Add the definitions of sync stype 0 (global completion barrier) and sync stype 0x10 (local ordering barrier) to barrier.h for use with the sync instruction. These types are defined by the MIPS Instruction Set since R2 of the architecture and are documented in document MD00087 table 6.5. Signed-off-by:
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Matt Redfearn authored
This code makes large use of barriers, which had quite vague descriptions. Update the comments to make the choice of barrier and reason for it more clear. Signed-off-by:
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Matt Redfearn authored
The check for whether a CPU required the FSB flush workaround previously required every CPU not requiring it to be whitelisted. That approach does not scale well as new CPUs are introduced so change the default from a WARN and returning an error to just returning 0. Any CPUs requiring the workaround can then be added to the blacklist. Signed-off-by:
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Matt Redfearn authored
MIPS CM version 3 removed the CPC_CL_OTHER register and instead the CM_CL_OTHER register is used to redirect the CPC_OTHER region. As such, we should not write the unimplmented register and can avoid the spinlock as well. These lock functions should aleady be called within the context of a mips_cm_{lock,unlock}_other pair ensuring the correct CPC_OTHER region will be accessed. Signed-off-by: -
Matt Redfearn authored
Checkpatch complains about use of bare unsigned type. Signed-off-by:
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Aaro Koskinen authored
Signed-off-by:
Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14250/Signed-off-by:
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Aaro Koskinen authored
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Aaro Koskinen authored
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Aaro Koskinen authored
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Aaro Koskinen authored
PHY access through the board helper is impossible with the current drivers, so delete this code. Signed-off-by:
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Aaro Koskinen authored
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Aaro Koskinen authored
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Aaro Koskinen authored
Leave that to actual ethernet/phy drivers. Signed-off-by:
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Aaro Koskinen authored
Delete legacy hack for broken bootloaders. The warning has been in kernel for several years, and if there are still users using such bootloaders, they can fix the boot by supplying a proper DTB. Signed-off-by:
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Masahiro Yamada authored
In many of clk_disable() implementations, it is a no-op for a NULL pointer input, but this is one of the exceptions. Making it treewide consistent will allow clock consumers to call clk_disable() without NULL pointer check. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by:
Florian Fainelli <f.fainelli@gmail.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: bcm-kernel-feedback-list@broadcom.com Cc: linux-arm-kernel@lists.infradead.org Patchwork: https://patchwork.linux-mips.org/patch/14264/Signed-off-by:
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Keith Busch authored
This patch removes creating a fake pci device in MIPS early config access and instead just uses the pci bus to get the same functionality. The struct pci_dev is too large to allocate on the stack, and was relying on compiler optimizations to remove its usage. Signed-off-by:
Keith Busch <keith.busch@intel.com> Reviewed-by:
Atsushi Nemoto <anemo@mba.ocn.ne.jp> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14253/Signed-off-by:
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Geert Uytterhoeven authored
Replace the custom minimal clock implementation for Toshiba TXx9 by a basic implementation using the Common Clock Framework. The only clocks that are provided are those needed by TXx9-specific drivers ("imbus" and "spi" (TX4938 only)), and their common parent clock "gbus". Other clocks can be added when needed. Signed-off-by:Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by:
Stephen Boyd <sboyd@codeaurora.org> Reviewed-by:
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Geert Uytterhoeven authored
While the custom minimal TXx9 clock implementation doesn't need or use clock (un)prepare calls (they are dummies if !CONFIG_HAVE_CLK_PREPARE), they are mandatory when using the Common Clock Framework. Hence add them, to prepare for the advent of CCF. Signed-off-by:
Guenter Roeck <linux@roeck-us.net> Cc: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Cc: Wim Van Sebroeck <wim@iguana.be> Cc: linux-clk@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-watchdog@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14238/Signed-off-by:
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Geert Uytterhoeven authored
txx9_gpio_init() calls gpiochip_add_data(), which fails with -ENOMEM as it is called too early in the boot process. This causes all subsequent GPIO operations to fail silently (before commit 54d77198 ("gpio: bail out silently on NULL descriptors") it printed the error message "gpiod_direction_output_raw: invalid GPIO" on RBTX49[23]7). Postpone all GPIO setup to .arch_init() time to fix this. Suggested-by:
Linus Walleij <linus.walleij@linaro.org> Cc: linux-mips@linux-mips.org Cc: linux-gpio@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14237/Signed-off-by:
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Geert Uytterhoeven authored
txx9_gpio_init() calls gpiochip_add_data(), which fails with -ENOMEM as it is called too early in the boot process. This causes all subsequent GPIO operations to fail silently. Postpone all GPIO setup to .arch_init() time to fix this. Suggested-by:
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Masahiro Yamada authored
Remove unneeded variables and assignments. Signed-off-by:
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Yang Ling authored
The patch adds RTC support for Loongson1C board, and enable the external crystal when the RTC is first powered up. Signed-off-by:
Yang Ling <gnaygnil@gmail.com> Cc: keguang.zhang@gmail.com Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14214/Signed-off-by:
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Paul Gortmaker authored
These files were only including module.h for exception table related functions. We've now separated that content out into its own file "extable.h" so now move over to that and avoid all the extra header content in module.h that we don't really need to compile these files. In the case of traps.c we can't dump the module.h include since it is also used to provide "print_modules". Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13934/Signed-off-by:
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Paul Gortmaker authored
The Kconfig currently controlling compilation of this code is: arch/mips/lantiq/Kconfig:config XRX200_PHY_FW arch/mips/lantiq/Kconfig: bool "XRX200 PHY firmware loader" ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. We don't replace module.h with init.h since the file doesn't need that. Signed-off-by:
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Paul Gortmaker authored
The Makefile entry controlling compilation of this code is: arch/mips/lantiq/xway/vmmc.o ---> arch/mips/lantiq/xway/Makefile:obj-y += vmmc.o ...meaning that it currently is not being built as a module by anyone. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We replace module.h with export.h since the file does actually use EXPORT_SYMBOL. Signed-off-by:
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Paul Gortmaker authored
The Makefile entry controlling compilation of this code is "obj-y" meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. We explicitly disallow a driver unbind, since that doesn't have a sensible use case anyway, and it allows us to drop the ".remove" code for non-modular drivers. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. We don't replace module.h with init.h since the file already has that. Signed-off-by:
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Paul Gortmaker authored
The Makefile entry controlling compilation of this code is "obj-y" meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. Since module_init translates to device_initcall in the non-modular case, the init ordering remains unchanged with this commit. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. Signed-off-by:
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Matt Redfearn authored
Commit 7eb8c99d ("MIPS: Delete smp-gic.c") removed the file from the Makefile and the option to build it from KConfig, but left the file itself floating in the tree. Remove the unused source file. Signed-off-by:
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Fabian Frederick authored
According to commit 9f6b6877 ("android: remove timed output/gpio driver") Signed-off-by:
Fabian Frederick <fabf@skynet.be> Cc: Rob Herring <robh@kernel.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13904/Signed-off-by:
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Markus Elfring authored
The field "owner" is set by the core. Thus delete an unneeded initialisation. Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Signed-off-by:
Markus Elfring <elfring@users.sourceforge.net> Cc: John Crispin <john@phrozen.org> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Julia Lawall <julia.lawall@lip6.fr> Cc: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Cc: linux-mips@linux-mips.org Cc: LKML <linux-kernel@vger.kernel.org> Cc: kernel-janitors@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13929/Signed-off-by:
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Matt Redfearn authored
The addition of VPE information to /proc/cpuinfo used to be in smp-mt.c. This file is not used by MIPS r6 kernels, so the Virtual Processor information was not present for these CPU types. Move the code to print VPE information into proc.c, add a case for MIPS r6 CPUS, and remove the block from smp-mt.c. Signed-off-by:
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Yang Ling authored
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