- 14 Aug, 2023 22 commits
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Rohit Agarwal authored
Add rpmhpd node and opps for this node to the SDX75 dts. Signed-off-by:
Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/1691415534-31820-9-git-send-email-quic_rohiagar@quicinc.com [bjorn: include qcom-rpmpd.h as well] Signed-off-by:
Bjorn Andersson <andersson@kernel.org>
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Rohit Agarwal authored
SDX75-idp features pmk8550, pmx75 and pm7550ba pmic, so include them. Signed-off-by:
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Rohit Agarwal authored
Add dtsi for pmx75 PMIC found in Qualcomm platforms. Signed-off-by:
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Rohit Agarwal authored
Add dtsi for pm7550ba PMIC found in Qualcomm platforms. Signed-off-by:
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Rohit Agarwal authored
Add pinctrl gpio dts node for pm7250b. Signed-off-by:
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Rohit Agarwal authored
Add SPMI node to SDX75 dtsi. Signed-off-by:
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Konrad Dybcio authored
The MMSS SMMU has its own power domain. Attach it so that we can drop the "keep it always-on" hack. Fixes: 05ce21b5 ("arm64: dts: qcom: msm8998: Configure the multimedia subsystem iommu") Reviewed-by:
Jeffrey Hugo <quic_jhugo@quicinc.com> Signed-off-by:
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Konrad Dybcio authored
The MMSS SMMU has been abusingly consuming the exposed RPM interconnect clock. Drop it. Fixes: 05ce21b5 ("arm64: dts: qcom: msm8998: Configure the multimedia subsystem iommu") Reviewed-by:
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Konrad Dybcio authored
SM8450 also exposes RPMh stats, hook them up for low power state monitoring. Signed-off-by:
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Konrad Dybcio authored
MMCC has its own GPLL0 legs - one for 1-1 and one for div-2 output. We've already been using the correct one in the non-div case, start doing so for the other one as well. Reviewed-by:
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Konrad Dybcio authored
GPUCC has its own GPLL0 leg, switch to it to allow shutting it down when it's unused. Reviewed-by:
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Bjorn Andersson authored
Merge additional MSM8998 GCC DeviceTree binding constants for use in the MSM8998 DeviceTree source.
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Konrad Dybcio authored
GPLL0 has two separate outputs to both GPUSS and MMSS: one that's 2-divided and one that runs at the same rate as the GPLL0 itself. Add the missing ones to the binding. Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
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Sridharan S N authored
Add support for wlan-2g LED on GPIO 36 and wps buttons on GPIO 35. Signed-off-by:
Sridharan S N <quic_sridsn@quicinc.com> Reviewed-by:
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Konrad Dybcio authored
Add the Qualcomm Pseudo-Random Number Generator. Signed-off-by:
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Bryan O'Donoghue authored
When we have no camera mezzanine attached it is still possible to run the test-pattern generator of the CSID block. As an example: media-ctl --reset yavta --no-query -w '0x009f0903 1' /dev/v4l-subdev2 yavta --list /dev/v4l-subdev2 media-ctl -d /dev/media0 -V '"msm_csid0":0[fmt:UYVY8_1X16/1920x1080 field:none]' media-ctl -l '"msm_csid0":1->"msm_ispif0":0[1]' media-ctl -d /dev/media0 -V '"msm_ispif0":0[fmt:UYVY8_1X16/1920x1080 field:none]' media-ctl -l '"msm_ispif0":1->"msm_vfe0_rdi0":0[1]' media-ctl -d /dev/media0 -V '"msm_vfe0_rdi0":0[fmt:UYVY8_1X16/1920x1080]' media-ctl -d /dev/media0 -p yavta -B capture-mplane --capture=5 -n 5 -I -f UYVY -s 1920x1080 --file=TPG-UYVU-1920x1080-000-#.bin /dev/video0 Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20230811234738.2859417-8-bryan.odonoghue@linaro.orgSigned-off-by:
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Bryan O'Donoghue authored
At the moment we define a single ov5640 sensor in the apq8016-sbc and disable that sensor. The sensor mezzanine for this is a D3 Engineering Dual ov5640 mezzanine card. Move the definition from the apq8016-sbc where it shouldn't be to a standalone dts. Enables the sensor by default, as we are adding a standalone mezzanine structure. Signed-off-by:
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Bryan O'Donoghue authored
There are two control lines controlled by GPIO going into ov5640 - Reset - Powerdown The driver and yaml expect "reset-gpios" and "powerdown-gpios" there has never been an "enable-gpios". Fixes: 39e0ce6c ("arm64: dts: qcom: apq8016-sbc: Add CCI/Sensor nodes") Signed-off-by:
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Bryan O'Donoghue authored
The driver for the ov5640 doesn't do a set-rate, instead it expects the clock to already be set at an appropriate rate. Similarly the yaml for ov5640 doesn't understand clock-frequency. Convert from clock-rate to assigned-clock and assigned-clock-rate to remediate. Signed-off-by:
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Bryan O'Donoghue authored
The yaml constraint for data-lanes is [1, 2] not [0, 2]. The driver itself doesn't do anything with the data-lanes declaration save count the number of specified data-lanes and calculate the link rate so, this change doesn't have any functional side-effects. Signed-off-by:
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Bryan O'Donoghue authored
The ov5640 driver expects DOVDD, AVDD and DVDD as regulator supply names. The ov5640 has depended on these names since the driver was committed upstream in 2017. Similarly apq8016-sbc.dtsi has had completely different regulator names since its own initial commit in 2020. Perhaps the regulators were left on in previous 410c bootloaders. In any case today on 6.5 we won't switch on the ov5640 without correctly naming the regulators. Fixes: 39e0ce6c ("arm64: dts: qcom: apq8016-sbc: Add CCI/Sensor nodes") Signed-off-by:
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Bryan O'Donoghue authored
Each CSIPHY in CAMMS maps to a port here in the dtsi, since the number of CSIPHYs is fixed per SoC define the 8916 ports for both available PHYs. Signed-off-by:
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- 11 Aug, 2023 13 commits
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Sricharan Ramabadhran authored
Add initial device tree support for the Qualcomm IPQ5018 SoC and rdp432-c2 board. Few things like 'reboot' does not work because, couple of more 'SCM' APIS are needed to clear some TrustZone settings. Those will be posted separately. Reviewed-by:
Varadarajan Narayanan <quic_varada@quicinc.com> Signed-off-by:
Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> Signed-off-by:
Sricharan Ramabadhran <quic_srichara@quicinc.com> Link: https://lore.kernel.org/r/1690533192-22220-6-git-send-email-quic_srichara@quicinc.comSigned-off-by:
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Sricharan Ramabadhran authored
Document the new ipq5018 SOC/board device tree bindings. Reviewed-by:
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Bjorn Andersson authored
Merge the IPQ5018 GCC Devicetree binding through a topic branch, in order to the the clock defines.
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Sricharan Ramabadhran authored
This patch adds support for the global clock controller found on the IPQ5018 based devices. Reviewed-by:
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Bartosz Golaszewski authored
Enable the second MAC on sa8775p-ride. Signed-off-by:
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Tested-by:
Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20230810080909.6259-10-brgl@bgdev.plSigned-off-by:
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Bartosz Golaszewski authored
Once we add a second ethernet node, the MDIO bus names will conflict unless we provide aliases. Add one for the existing ethernet node. Signed-off-by:
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Bartosz Golaszewski authored
For improved readability order the aliases alphabetically for sa8775p-ride. Signed-off-by:
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Bartosz Golaszewski authored
Add a second SGMII PHY that will be used by EMAC1 on sa8775p-ride. Signed-off-by:
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Bartosz Golaszewski authored
We'll be adding a second SGMII PHY on the same MDIO bus, so let's index the first one for better readability. Signed-off-by:
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Bartosz Golaszewski authored
Device-tree bindings for MDIO define per-PHY reset-gpios as well as a global reset-gpios property at the MDIO node level which controls all devices on the bus. The latter is most likely a workaround for the chicken-and-egg problem where we cannot read the ID of the PHY before bringing it out of reset but we cannot bring it out of reset until we've read its ID. I have proposed a comprehensive solution for this problem in 2020 but it never got upstream. We do however have workaround in place which allows us to hard-code the PHY id in the compatible property, thus skipping the ID scanning. Let's make the device-tree for sa8775p-ride slightly more correct by moving the reset-gpios property to the PHY node with its ID put into the PHY node's compatible. Link: https://lore.kernel.org/all/20200622093744.13685-1-brgl@bgdev.pl/Signed-off-by:
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Bartosz Golaszewski authored
Enable the second SerDes PHY on sa8775p-ride development board. Signed-off-by:
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Bartosz Golaszewski authored
Add a node for the second MAC on sa8775p platforms. Signed-off-by:
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Bartosz Golaszewski authored
Add a node for the SerDes PHY used by EMAC1 on sa8775p-ride. Signed-off-by:
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- 10 Aug, 2023 2 commits
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Bryan O'Donoghue authored
Enable CAMSS on the standard RB3 as it is possible to run the test pattern generator (TPG) without any populated ports/endpoints. media-ctl --reset yavta --no-query -w '0x009f0903 9' /dev/v4l-subdev4 yavta --list /dev/v4l-subdev4 media-ctl -d /dev/media0 -V '"msm_csid0":0[fmt:SGRBG10_1X10/3280x2464]' media-ctl -d /dev/media0 -V '"msm_vfe0_rdi0":0[fmt:SGRBG10_1X10/3280x2464]' media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]' media-ctl -d /dev/media0 -p yavta -B capture-mplane --capture=5 -n 5 -I -f SGRBG10P -s 3280x2464 --file=TPG-SGRBG10-3280x2464-000-#.bin /dev/video2 Signed-off-by:
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Eric Chanudet authored
SA8540P-ride is one of the Qualcomm platforms that does not have access to UEFI runtime services and on which the RTC registers are read-only, as described in: https://lore.kernel.org/all/20230202155448.6715-1-johan+linaro@kernel.org/ Reserve four bytes in one of the PMIC registers to hold the RTC offset the same way as it was done for sc8280xp-crd which has similar limitations: commit e67b4558 ("arm64: dts: qcom: sc8280xp-crd: enable rtc") On SA8540P-ride, the register bank SDAM6 of the first PMIC is not writable. Following recommendations provided during the review, use SDAM2 from the second PMIC at offset 0xa0 instead. Reviewed-by:
Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by:
Eric Chanudet <echanude@redhat.com> Link: https://lore.kernel.org/r/20230809203506.1833205-1-echanude@redhat.comSigned-off-by:
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- 04 Aug, 2023 3 commits
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Richard Acayan authored
Add the coefficients for the CPU frequencies to aid in frequency scaling. Profiling setup: - freqbench (https://github.com/kdrag0n/freqbench) - LineageOS kernel, android_kernel_google_msm-4.9 - recommended configuration options by freqbench - disabled options that require clang or 32-bit compilers - mmc governor switched from simple_ondemand to powersave Frequency domains: cpu1 cpu6 Offline CPUs: cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 Sampling power every 1000 ms Baseline power usage: 445 mW ===== CPU 1 ===== Frequencies: 300 576 748 998 1209 1324 1516 1612 1708 300: 1114 3.7 C/MHz 43 mW 11.6 J 25.8 I/mJ 269.4 s 576: 2138 3.7 C/MHz 51 mW 7.1 J 42.2 I/mJ 140.3 s 748: 2780 3.7 C/MHz 67 mW 7.3 J 41.3 I/mJ 107.9 s 998: 3706 3.7 C/MHz 73 mW 5.9 J 51.1 I/mJ 80.9 s 1209: 4490 3.7 C/MHz 86 mW 5.7 J 52.2 I/mJ 66.8 s 1324: 4918 3.7 C/MHz 90 mW 5.5 J 54.6 I/mJ 61.0 s 1516: 5631 3.7 C/MHz 103 mW 5.5 J 54.9 I/mJ 53.3 s 1612: 5987 3.7 C/MHz 109 mW 5.5 J 55.0 I/mJ 50.1 s 1708: 6344 3.7 C/MHz 126 mW 5.9 J 50.5 I/mJ 47.3 s ===== CPU 6 ===== Frequencies: 300 652 825 979 1132 1363 1536 1747 1843 1996 300: 1868 6.2 C/MHz 53 mW 8.5 J 35.2 I/mJ 160.6 s 652: 4073 6.2 C/MHz 96 mW 7.1 J 42.4 I/mJ 73.7 s 825: 5132 6.2 C/MHz 117 mW 6.9 J 43.7 I/mJ 58.5 s 979: 6099 6.2 C/MHz 151 mW 7.4 J 40.4 I/mJ 49.2 s 1132: 7071 6.2 C/MHz 207 mW 8.8 J 34.1 I/mJ 42.4 s 1363: 8482 6.2 C/MHz 235 mW 8.3 J 36.1 I/mJ 35.4 s 1536: 9578 6.2 C/MHz 287 mW 9.0 J 33.3 I/mJ 31.3 s 1747: 10892 6.2 C/MHz 340 mW 9.4 J 32.0 I/mJ 27.6 s 1843: 11471 6.2 C/MHz 368 mW 9.6 J 31.1 I/mJ 26.2 s 1996: 12425 6.2 C/MHz 438 mW 10.6 J 28.3 I/mJ 24.2 s Signed-off-by:
Richard Acayan <mailingradian@gmail.com> Link: https://lore.kernel.org/r/20230802011548.387519-10-mailingradian@gmail.comSigned-off-by:
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Richard Acayan authored
Add CPU frequency scaling, and also add the corresponding memory and cache bandwidths for each frequency. Signed-off-by:
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Richard Acayan authored
Add the interconnect node for L3 cache on SDM670. Signed-off-by:
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