- 22 Aug, 2017 22 commits
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Yong Li authored
On AST2500, the hardware strap register(SCU70) only accepts write ‘1’, to clear it to ‘0’, must set bits(write ‘1’) to SCU7C Signed-off-by:
Yong Li <sdliyong@gmail.com> Reviewed-by:
Andrew Jeffery <andrew@aj.id.au> Tested-by:
Linus Walleij <linus.walleij@linaro.org>
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Icenowy Zheng authored
The pin controller of Allwinner H5 has three IRQ banks, however in old versions of drivers and device trees, only two are set, which makes PG bank IRQ not available. If it's directly set to 3, the old device trees will fail to boot. Add a workaround (and a warning) for older device trees, and allow new device trees to use correct 3 IRQ banks. Fixes: 838adb57 ("drivers: pinctrl: add driver for Allwinner H5 SoC") Signed-off-by:
Icenowy Zheng <icenowy@aosc.io> Acked-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
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Rushikesh S Kadam authored
The fix prevents unintended wakes from second level GPIO pin interrupts. On some Intel Kabylake platforms, it is observed that GPIO pin interrupts can wake the platform from suspend-to-idle, even though the IRQ is not configured as IRQF_NO_SUSPEND or enable_irq_wake(). This can cause undesired wakes on Mobile devices such as Laptops and Chromebook devices. For example a headset jack insertion is not a desired wake source on Chromebook devices. The pinctrl-intel (GPIO controller) driver implements a "Shared IRQ" model. All GPIO pin interrupts are OR'ed and mapped to a first level IRQ14 (or IRQ15). The driver registers an irq_chip struct and maps an irq_domain for the GPIO pin interrupts. The IRQ14 handler demuxes and calls the second level IRQ for the respective pin. In the suspend entry flow, at suspend_noirq stage, the kernel disables IRQs that are not marked for wake. The pinctrl-intel driver does not implement a irq_disable() callback (to take advantage of lazy disabling). The pinctrl-intel GPIO interrupts are not disabled in hardware during suspend entry, and thus are able to wake the SoC out of suspend-to-idle. This patch sets the IRQCHIP_MASK_ON_SUSPEND flag for the GPIO irq_chip, to disable the second level interrupts at suspend_noirq stage via the irq_mask callbacks. The irq_mask callback disables the IRQs in hardware by programming the corresponding GPIO pad registers. Only IRQs that are not marked for wake are disabled. Signed-off-by:
Rushikesh S Kadam <rushikesh.s.kadam@intel.com> Acked-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-and-tested-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by:
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Julia Lawall authored
These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by:
Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by:
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Julia Lawall authored
These structures are only stored in fields of a pinctrl_desc structure (confops and pctlops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
These structures are only stored in fields of a pinctrl_desc structure (pctlops and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
This pinmux_ops structure is only stored in the const pmxops field of a pinctrl_desc structure. Make the pinmux_ops structure const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
These structures are only stored in fields of a pinctrl_desc structure (pctlops and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
These structures are only stored in fields of a pinctrl_desc structure (pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
These structures are only stored in fields of a pinctrl_desc structure (pctlops and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by:
Baruch Siach <baruch@tkos.co.il> Signed-off-by:
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Julia Lawall authored
These structures are only stored in fields of a pinctrl_desc structure (pctlops and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
This pinmux_ops structure is only stored in the const pmxops field of a pinctrl_desc structure. Make the pinmux_ops structure const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by:
Patrice Chotard <patrice.chotard@st.com> Signed-off-by:
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Julia Lawall authored
This pinconf_ops structure is only stored in the const pinconf_ops field of a pinctrl_desc structure. Make the pinconf_ops structure const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
This pinctrl_ops structure is only stored in the const pctlops field of a pinctrl_desc structure. Make the pinctrl_ops structure const as well. Done with the help of Coccinelle. Signed-off-by:
Lars Persson <lars.persson@axis.com> Signed-off-by:
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Julia Lawall authored
This pinconf_ops structure is only stored in the const confops field of a pinctrl_desc structure. Make the pinconf_ops structure const as well. Done with the help of Coccinelle. Signed-off-by:
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Katsuhiro Suzuki authored
The UniPhier LD11/20 SoC audio core use following 8 pins: AO1IEC, AO1ARC, AO1DACCK, AO1BCK, AO1LRCK, AO1D[0-2] Signed-off-by:
Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
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Gustavo A. R. Silva authored
platform_get_irq() returns an error code, but the pinctrl-amd driver ignores it and always returns -EINVAL. This is not correct and, prevents -EPROBE_DEFER from being propagated properly. Print and propagate the return value of platform_get_irq on failure. This issue was detected with the help of Coccinelle. Signed-off-by:
Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by:
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- 18 Aug, 2017 1 commit
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Linus Walleij authored
This patch: - Adds myself as comaintainer for the Gemini. - Adds the Gemini main bindings to the file list. - Adds the pin controller plus bindings to the Gemini file list. - Fixes up the path of the RTC binding and driver. Acked-by:
Hans Ulli Kroll <ulli.kroll@googlemail.com> Signed-off-by:
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- 15 Aug, 2017 2 commits
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Fenglin Wu authored
Add property "qcom,dtest-buffer" to specify which dtest rail to feed when the pin is configured as a digital input. Signed-off-by:
Fenglin Wu <fenglinw@codeaurora.org> Acked-by:
Rob Herring <robh@kernel.org> Acked-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
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Fenglin Wu authored
GPIO LV (low voltage)/MV (medium voltage) subtypes have different features and register mappings than 4CH/8CH subtypes. Add support for LV and MV subtypes. Signed-off-by:
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- 14 Aug, 2017 15 commits
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Linus Walleij authored
Merge tag 'samsung-pinctrl-4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl driver changes for v4.14: 1. Fix NULL pointer dereference on S3C24XX. This was reported some time ago and unfortunately it took few releases to fix. 2. Fix invalid register offset used for external interrupts on Exynos5433. This was caused by the same commit as above, although on different path. 3. Consolidate between drivers and bindings the defines for pin mux functions. 4. Minor code improvements.
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Linus Walleij authored
This adds a pin control (only multiplexing) driver for the Gemini SoC so we can sort out this complex platform in an orderly manner. This driver will detect the chip/package version as SL3512 or SL3516 (also known as CS3512 and CS3516 etc) and register the apropriate pin set. Signed-off-by: -
Masahiro Yamada authored
pinconf_set_config() is called by pinctrl_gpio_set_config(). If a GPIO driver is backed by a pinctrl driver and it does not support .pin_config_set() hook, it causes NULL pointer dereference. Fixes: 15381bc7 ("pinctrl: Allow configuration of pins from gpiolib based drivers") Signed-off-by:
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Mika Westerberg authored
This driver adds pinctrl/GPIO support for Intel Denverton SoC. The GPIO controller is based on the same hardware design that is already used in Intel Sunrisepoint so we leverage the core driver here. Signed-off-by:
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Masahiro Yamada authored
Sparse reports "warning: incorrect type in assignment (different address spaces)". Signed-off-by:
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Masahiro Yamada authored
Sparse reports "warning: incorrect type in return expression (different address spaces)" because nmk_gpio_populate_chip() is supposed to return (struct nmk_gpio_chip *) whereas devm_ioremap_resource() returns (void __iomem *). ERR_CAST() is needed to fix the warning. Signed-off-by:
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Masahiro Yamada authored
Detected by sparse. Signed-off-by:
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Masahiro Yamada authored
Detected by sparse. Signed-off-by:
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Masahiro Yamada authored
Since commit 58957d2e ("pinctrl: Widen the generic pinconf argument from 16 to 24 bits"), the generic pinconf arguments are handled by u32. UniPhier pinctrl drivers do not support debouncing, so u16 is working, but align the argument type to u32 for consistency. Signed-off-by:
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Icenowy Zheng authored
The V3s pin controller doesn't have the bank 0 (starts at address 0x200), which is like A33. However, this is not worked around when developing the driver, which makes IRQ not working. Fix the IRQ bank base. Fixes: 56d9e4a7 ("pinctrl: sunxi: add driver for V3s SoC") Signed-off-by:
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Masahiro Yamada authored
Update subsystem wide for consistency. Signed-off-by:
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Zhiyong Tao authored
The commit adds mt2712 compatible node in binding document. Signed-off-by:
Zhiyong Tao <zhiyong.tao@mediatek.com> Acked-by:
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Sergei Shtylyov authored
of_irq_to_resource() has recently been fixed to return negative error #'s along with 0 in case of failure, however the ST driver still only regards 0 as failure indication -- fix it up. Fixes: 7a4228bb ("of: irq: use of_irq_get() in of_irq_to_resource()") Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
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Linus Walleij authored
The Cortina Gemini pin controller uses the standard pin control bindings for muxing functions with groups so these bindings should be entirely uncontroversial. Cc: devicetree@vger.kernel.org Signed-off-by: -
Andy Yan authored
Some pins like i2c SCL/SDA need the schmitt input function to avoid crosstalk problems. Signed-off-by:
Andy Yan <andy.yan@rock-chips.com> Reviewed-by:
Heiko Stuebner <heiko@sntech.de> Signed-off-by:
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