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  1. 18 Sep, 2012 1 commit
  2. 23 Aug, 2012 1 commit
  3. 10 Jul, 2012 2 commits
    • Bjorn Helgaas's avatar
      PCI: reimplement P2P bridge 1K I/O windows (Intel P64H2) · 2b28ae19
      Bjorn Helgaas authored
      9d265124 and 15a260d5 added quirks for P2P bridges that support
      I/O windows that start/end at 1K boundaries, not just the 4K boundaries
      defined by the PCI spec.  For details, see the IOBL_ADR register and the
      EN1K bit in the CNF register in the Intel 82870P2 (P64H2).
      
      These quirks complicate the code that reads P2P bridge windows
      (pci_read_bridge_io() and pci_cfg_fake_ranges()) because the bridge
      I/O resource is updated in the HEADER quirk, in pci_read_bridge_io(),
      in pci_setup_bridge(), and again in the FINAL quirk.  This is confusing
      and makes it impossible to reassign the bridge windows after FINAL
      quirks are run.
      
      This patch adds support for 1K windows in the generic paths, so the
      HEADER quirk only has to enable this support.  The FINAL quirk, which
      used to undo damage done by pci_setup_bridge(), is no longer needed.
      
      This removes "if (!res->start) res->start = ..." from pci_read_bridge_io();
      that was part of 9d265124 to avoid overwriting the resource filled in
      by the quirk.  Since pci_read_bridge_io() itself now knows about
      granularity, the quirk no longer updates the resource and this test is no
      longer needed.
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      2b28ae19
    • Bjorn Helgaas's avatar
      PCI: leave MEM and IO decoding disabled during 64-bit BAR sizing, too · bbffe435
      Bjorn Helgaas authored
      After 253d2e54, we disable MEM and IO decoding for most devices while we
      size 32-bit BARs.  However, we restore the original COMMAND register before
      we size the upper 32 bits of 64-bit BARs, so we can still cause a conflict.
      
      This patch waits to restore the original COMMAND register until we're
      completely finished sizing the BAR.
      
      Reference: https://lkml.org/lkml/2007/8/25/154Acked-by: default avatarJacob Pan <jacob.jun.pan@linux.intel.com>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      bbffe435
  4. 09 Jul, 2012 1 commit
    • Bjorn Helgaas's avatar
      PCI: allow P2P bridge windows starting at PCI bus address zero · 5dde383e
      Bjorn Helgaas authored
      cd81e1ea added checks that prevent us from using P2P bridge windows
      that start at PCI bus address zero.  The reason was to "prevent us from
      overwriting resources that are unassigned."
      
      But generic code should allow address zero in both BARs and bridge
      windows, so I think that commit was a mistake.
      
      Windows at bus address zero are legal and likely to exist on machines with
      an offset between bus addresses and CPU addresses.  For example, in the
      following hypothetical scenario, the bridge at 00:01.0 has a window at bus
      address zero and the device at 01:00.0 has a BAR at bus address zero, and
      I think both are perfectly valid:
      
          PCI host bridge to bus 0000:00
          pci_bus 0000:00: root bus resource [mem 0x100000000-0x1ffffffff] (bus address [0x00000000-0xffffffff])
          pci 0000:00:01.0: PCI bridge to [bus 01]
          pci 0000:00:01.0:   bridge window [mem 0x100000000-0x100ffffff]
          pci 0000:01:00.0: reg 10: [mem 0x100000000-0x100ffffff]
      Acked-by: default avatarYinghai Lu <yinghai@kernel.org>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      5dde383e
  5. 20 Jun, 2012 1 commit
    • Bjorn Helgaas's avatar
      PCI: fix P2P bridge I/O port window sign extension · 8f38eaca
      Bjorn Helgaas authored
      On P2P bridges with 32-bit I/O decoding, we incorrectly sign-extended
      windows starting at 0x80000000 or above.  In "base |= (io_base_hi << 16)",
      "io_base_hi" is promoted to a signed int before being extended to an
      unsigned long.
      
      This would cause a window starting at I/O address 0x80000000 to be
      treated as though it started at 0xffffffff80008000 instead, which
      should cause "no compatible bridge window" errors when we enumerate
      devices using that I/O space.
      
      The mmio and mmio_pref casts are not strictly necessary, but without
      them, correctness depends on the types of the PCI_MEMORY_RANGE_MASK and
      PCI_PREF_RANGE_MASK constants, which are not obvious from reading the
      local code.
      
      Found by Coverity (CID 138747 and CID 138748).
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      8f38eaca
  6. 13 Jun, 2012 8 commits
  7. 30 Apr, 2012 4 commits
  8. 20 Mar, 2012 1 commit
  9. 24 Feb, 2012 7 commits
    • Yinghai Lu's avatar
      PCI: Move "pci reassigndev resource alignment" out of quirks.c · 2069ecfb
      Yinghai Lu authored
      This isn't really a quirk; calling it directly from pci_add_device makes
      more sense.
      Signed-off-by: default avatarYinghai Lu <yinghai@kernel.org>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      2069ecfb
    • Bjorn Helgaas's avatar
      PCI: collapse pcibios_resource_to_bus · fb127cb9
      Bjorn Helgaas authored
      Everybody uses the generic pcibios_resource_to_bus() supplied by the core
      now, so remove the ARCH_HAS_GENERIC_PCI_OFFSETS used during conversion.
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      fb127cb9
    • Bjorn Helgaas's avatar
      PCI: add generic pcibios_resource_to_bus() · 36a66cd6
      Bjorn Helgaas authored
      This replaces the generic versions of pcibios_resource_to_bus() and
      pcibios_bus_to_resource() in asm-generic/pci.h with versions that use
      pci_resource_to_bus() and pci_bus_to_resource().
      
      The replacements are equivalent except that they can apply host
      bridge window offsets when the arch has supplied them by using
      pci_add_resource_offset().
      
      Each arch can convert to using pci_add_resource_offset() individually by
      removing its device resource fixups from pcibios_fixup_bus() and supplying
      ARCH_HAS_GENERIC_PCI_OFFSETS.  ARCH_HAS_GENERIC_PCI_OFFSETS can be removed
      after all have converted.
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      36a66cd6
    • Bjorn Helgaas's avatar
      PCI: convert bus addresses to resource when reading BARs · 5bfa14ed
      Bjorn Helgaas authored
      Some PCI host bridges translate CPU addresses to PCI bus addresses.
      Previously, we initialized pci_dev resources with PCI bus addresses,
      then converted them to CPU addresses later in arch-specific code
      (pcibios_fixup_resources()), which leaves a window of time where the
      pci_dev resources are incorrect.
      
      This patch adds support in the core for this address translation.
      When the arch creates the root bus, it can supply the host bridge
      address translation information, and the core can use it to set the
      pci_dev resources correctly from the beginning.
      
      This gives us a way to fix the problem that quirks that run between device
      discovery and pcibios_fixup_resources() fail because they use pci_dev
      resources that haven't been converted.  The reference below is to one
      such problem that affected ARM and ia64.
      
      Note that this patch has no effect until an arch starts using
      pci_add_resource_offset() with a non-zero offset: before that, all
      all host bridge windows have a zero offset and pci_bus_to_resource()
      copies the pci_bus_region directly to the struct resource.
      
      Reference: https://lkml.org/lkml/2009/10/12/405Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      5bfa14ed
    • Bjorn Helgaas's avatar
      PCI: add struct pci_host_bridge_window with CPU/bus address offset · 0efd5aab
      Bjorn Helgaas authored
      Some PCI host bridges apply an address offset, so bus addresses on PCI are
      different from CPU addresses.  This patch adds a way for architectures to
      tell the PCI core about this offset.  For example:
      
          LIST_HEAD(resources);
          pci_add_resource_offset(&resources, host->io_space, host->io_offset);
          pci_add_resource_offset(&resources, host->mem_space, host->mem_offset);
          pci_scan_root_bus(parent, bus, ops, sysdata, &resources);
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      0efd5aab
    • Bjorn Helgaas's avatar
      PCI: add struct pci_host_bridge and a list of all bridges found · 5a21d70d
      Bjorn Helgaas authored
      This adds a list of all PCI host bridges we find and a way to look up
      the host bridge from a pci_dev.
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      5a21d70d
    • Bjorn Helgaas's avatar
      PCI: don't publish new root bus until it's fully initialized · a5390aa6
      Bjorn Helgaas authored
      When pci_create_root_bus() adds the new struct pci_bus to the global
      pci_root_buses list, the bus becomes visible to other parts of the
      kernel, so it should be fully initialized.
      
      This patch delays adding the bus to the pci_root_buses list until after
      all the struct pci_bus initialization is finished.
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      a5390aa6
  10. 23 Feb, 2012 2 commits
    • Yinghai Lu's avatar
      PCI: fix memleak for pci dev removing during hotplug · f796841e
      Yinghai Lu authored
      unreferenced object 0xffff880276d17700 (size 64):
        comm "swapper/0", pid 1, jiffies 4294897182 (age 3976.028s)
        hex dump (first 32 bytes):
          00 00 00 00 00 00 00 00 18 f9 de 76 02 88 ff ff  ...........v....
          10 00 00 00 0e 00 00 00 0f 28 40 00 00 00 00 00  .........(@.....
        backtrace:
          [<ffffffff81c8aede>] kmemleak_alloc+0x26/0x43
          [<ffffffff811385f0>] __kmalloc+0x121/0x183
          [<ffffffff813cf821>] pci_add_cap_save_buffer+0x35/0x7c
          [<ffffffff813d12b7>] pci_allocate_cap_save_buffers+0x1d/0x65
          [<ffffffff813cdb52>] pci_device_add+0x92/0xf1
          [<ffffffff81c8afe6>] pci_scan_single_device+0x9f/0xa1
          [<ffffffff813cdbd2>] pci_scan_slot.part.20+0x21/0x106
          [<ffffffff813cdce2>] pci_scan_slot+0x2b/0x35
          [<ffffffff81c8dae4>] __pci_scan_child_bus+0x51/0x107
          [<ffffffff81c8d75b>] pci_scan_bridge+0x376/0x6ae
          [<ffffffff81c8db60>] __pci_scan_child_bus+0xcd/0x107
          [<ffffffff81c8dbab>] pci_scan_child_bus+0x11/0x2a
          [<ffffffff81cca58c>] pci_acpi_scan_root+0x18b/0x21c
          [<ffffffff81c916be>] acpi_pci_root_add+0x1e1/0x42a
          [<ffffffff81406210>] acpi_device_probe+0x50/0x190
          [<ffffffff814a0227>] really_probe+0x99/0x126
      
      Need to free saved_buffer for capabilities.
      Signed-off-by: default avatarYinghai Lu <yinghai@kernel.org>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      f796841e
    • Yinghai Lu's avatar
      PCI: Fix device class print out · 2dd8ba92
      Yinghai Lu authored
      Found debug print of class is shifted.
      
      | pci 0000:f8:15.2: [8086:2b56] type 0 class 0x000600
      
      Code is trying to print class with 6 digits, but use shifted class with
      4 digits valid value as variable.
      
      Change to original dev->class directly.
      
      Also remove not needed calculating of local variable class, because it
      will be updated after pci_fixup_device(pci_fixup_early...)
      
      Also unify type print out when class and header is not matched.
      Signed-off-by: default avatarYinghai Lu <yinghai@kernel.org>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      2dd8ba92
  11. 14 Feb, 2012 3 commits
  12. 10 Feb, 2012 1 commit
    • Yinghai Lu's avatar
      PCI: workaround hard-wired bus number V2 · 71f6bd4a
      Yinghai Lu authored
      Fixes PCI device detection on IBM xSeries IBM 3850 M2 / x3950 M2
      when using ACPI resources (_CRS).
      This is default, a manual workaround (without this patch)
      would be pci=nocrs boot param.
      
      V2: Add dev_warn if the workaround is hit. This should reveal
      how common such setups are (via google) and point to possible
      problems if things are still not working as expected.
      -> Suggested by Jan Beulich.
      
      Cc: stable@vger.kernel.org
      Tested-by: garyhade@us.ibm.com
      Signed-off-by: default avatarYinghai Lu <yinghai.lu@oracle.com>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      71f6bd4a
  13. 06 Jan, 2012 8 commits