- 27 Oct, 2020 40 commits
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Alex Deucher authored
Stop registering the SMU i2c bus on navi1x. This leads to instability issues when userspace processes mess with the bus and also seems to cause display stability issues in some cases. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1314 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1341Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Not used any more. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Huang Rui authored
This patch is to add vangogh apu flag to support more kickers that belongs vangogh series. Signed-off-by:
Huang Rui <ray.huang@amd.com> Acked-by:
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Evan Quan authored
With this, for multiple monitors in sync(e.g. with the same model), mclk switching will be allowed. That helps saving some idle power on some ASICs(e.g. Polaris). Signed-off-by:
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Evan Quan authored
Check chip family also to avoid wrong identification. V2: use the correct macro without AMDGPU prefix Signed-off-by:
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Evan Quan authored
As this is already performed in smu7_set_power_state_tasks(). Signed-off-by:
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Evan Quan authored
Reconfigure smc display settings on vbitimeout change. Signed-off-by:
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Evan Quan authored
Correct the mclk switching setting for multiple displays. Signed-off-by:
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Evan Quan authored
Enable watermark table setting for Polaris. Signed-off-by:
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Evan Quan authored
Fulfill Polaris get_clock_by_type_with_latency(). Signed-off-by:
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Evan Quan authored
Correct Polaris10 setup. Signed-off-by:
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Evan Quan authored
Correct Polaris smc boot level setup. Signed-off-by:
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Evan Quan authored
Correct Polaris10 pcie spc cap setting. Signed-off-by:
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Evan Quan authored
Correct Polaris10 clk/voltage dependence setup. Signed-off-by:
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Evan Quan authored
Populate the correct highest vddc setting on Polaris. Signed-off-by:
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Evan Quan authored
Correct Polaris10 sclk/mclk dpm enablement. Signed-off-by:
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Evan Quan authored
Correct Polaris10 smc voltage controller setup. Signed-off-by:
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Evan Quan authored
Correct Polaris10 platformcaps setup. Signed-off-by:
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Evan Quan authored
Correct Polaris VRconfig setting. Signed-off-by:
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Evan Quan authored
Correct Polaris10 vddc phase control. Signed-off-by:
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Evan Quan authored
Correct Polaris10 avfs fuse setting. Signed-off-by:
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Evan Quan authored
Correct Polaris DIDT enablement. Signed-off-by:
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Evan Quan authored
Correct powertune table setup for Polaris. Signed-off-by:
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Evan Quan authored
Correct sclk/mclk SS support checks. Signed-off-by:
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Evan Quan authored
Add VR shared rail info. Signed-off-by:
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Evan Quan authored
Add mc register table initialization. Signed-off-by:
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Evan Quan authored
Enable edc controller table setting. Signed-off-by:
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Evan Quan authored
Only if the ZeroRPM feature is supported. Signed-off-by:
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Evan Quan authored
By using the saved copy of ro_range_maximum and ro_range_minimum. Correct the setting for "LdoRefSel". Signed-off-by:
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Evan Quan authored
Make the settings more precise. Signed-off-by:
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Evan Quan authored
By moving that in atomfw_read_efuse(). Signed-off-by:
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Evan Quan authored
Programming AC Timing Parameters is only dependent on MCLK. No need to nest loop for each SCLK DPM level. Signed-off-by:
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Evan Quan authored
Instead of sharing the fan table setup with Tonga, Polaris has its own fan table setup. Signed-off-by:
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Evan Quan authored
This is for some special Polaris10 ASICs. Signed-off-by:
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Evan Quan authored
Correct polaris CG_ACLK_CNTL setting. Signed-off-by:
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Evan Quan authored
As this is not needed for polaris. Signed-off-by:
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Evan Quan authored
Add missing VRHotLevel setting. Signed-off-by:
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Evan Quan authored
Set the BootLinkLevel as the max level. Signed-off-by:
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Evan Quan authored
Correct the setting for "ActivityLevel". V2: rich the comment Signed-off-by:
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Evan Quan authored
Correct the settings for "StutterEnable" and "EnabledForActivity". Signed-off-by:
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