- 02 Jun, 2015 8 commits
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Hans de Goede authored
The ga10h is an 10" tablet with an A33 or A23 soc, 1G RAM, 8G or 16G nand, sdio wifi, 2 micro usb ports, 1 otg and 1 host and 1 micro sd slot. This commit adds a dts file for the v1.1 pcb with an a33 soc. Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Chen-Yu Tsai authored
The SinA33 is a core/SDK development board by Sinlinx. The core board does not have any connectors or pads, other than the pads used to connect it to the SDK board. The core board only has the A33 SoC, 2 RAM chips, an eMMC flash chip, the AXP223 PMIC, and supporting discrete components. eMMC is optional. The SDK board has a USB host, USB OTG, volume control and home buttons, audio input/output jacks, a micro-SD slot, camera and SDIO expansion headers, an LCD connector, and a GPIO expansion header, which has UARTs, MIPI DSI and I2C available. Only UART0 is enabled though. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
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Chen-Yu Tsai authored
The A33 adds an additional pinmux option for uart0 on the PB pins. This was not present on the A23. Nor is it available on the H3, which does not have the PB pingroup. Signed-off-by:
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Chen-Yu Tsai authored
mmc2 is mostly used with eMMC flash chips, as an alternative to raw NAND flash chips. 8 bit mmc is commonly used. Signed-off-by:
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Hans de Goede authored
Add an usb_clk node for a23/a33. Signed-off-by:
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Vishnu Patekar authored
ET-Q8_A33 is A33 based cheap tablet in common Q8 format. It has 512MB RAM, 4GB Nand, 7" Display, RDA5900P wifi, GSL1680 touch, etc. Signed-off-by:
Vishnu Patekar <vishnupatekar0510@gmail.com> Signed-off-by:
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Vishnu Patekar authored
Add a dtsi file for use with a33 based boards based on the new sun8i-a23-a33.dtsi file. Signed-off-by:
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Vishnu Patekar authored
Rename sun8i-a23.dtsi to sun8i-a23-a33.dtsi as the base dtsi for the A33 is 99% the same and add a new sun8i-a23.dtsi including sun8i-a23-a33.dtsi and setting the few things not shared with the A33 (mbus-clk, pio compatible and interrupts). Signed-off-by:
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- 01 Jun, 2015 8 commits
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Maxime Ripard authored
The A20 has a few SRAM that can be mapped either to a device or to the CPU, with the mapping being controlled by a SRAM controller. Add the SRAM controller, the SRAM that it drives and the section that can be used by the various devices. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Acked-by:
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Maxime Ripard authored
The A10s and A13 have a few SRAM that can be mapped either to a device or to the CPU, with the mapping being controlled by a SRAM controller. Add the SRAM controller, the SRAM that it drives and the section that can be used by the various devices. Signed-off-by:
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Maxime Ripard authored
The A10 has a few SRAM that can be mapped either to a device or to the CPU, with the mapping being controlled by a SRAM controller. Add the SRAM controller, the SRAM that it drives and the section that can be used by the various devices. Signed-off-by:
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Maxime Ripard authored
This patch reverts commit ccb4ada2 ("ARM: dts: sun7i: Add A20 SRAM and SRAM controller"), commit e6f51e4b ("ARM: dts: sun5i: Add A13 and A10s SRAM and SRAM controller") and commit 6d92b80f ("ARM: dts: sun4i: Add A10 SRAM and SRAM controller"). The bindings have been changed in the SRAM driver, and we need to change the DT accordingly. Signed-off-by:
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Chen-Yu Tsai authored
On A80 there are 2 watchdogs, one in the main block, and one in the R (special) block. We do not have information on the R block watchdog, other than the register layout is the same, and the interrupt number. Both are able to reset the whole system. Add the main watchdog, in case the R block is used for special purposes like running an RTOS. Signed-off-by:
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Michael Ring authored
The BananaPro uses uart4 for the default rx/tx pins on the 40 pins connector, so enable uart4. Uart2 is also available at the bananapro io-pins, but like on the bananapi the primary function of the pins is to act as gpios, see: http://forum.lemaker.org/forum.php?mod=viewthread&tid=10852 Remove the uart2 node, people who want to use uart2 can do so with a devicetree-overlay. Signed-off-by:
Michael Ring <mail@michael-ring.org> [hdegoede@redhat.com: Remove uart2 node] Signed-off-by:
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Michael Ring authored
Some boards (e.g. the BananaPro) use alternative pins for uart4, add a pinmux entry for these. Signed-off-by:
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Maxime Ripard authored
The A23 Evaluation Board has an MMC slot, two UARTs, NAND, a few display connectors (RGB, MIPI, LVDS), a mini-PCIE slot, USB host and OTG and a bunch of embedded sensors. Signed-off-by:
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- 10 May, 2015 4 commits
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Maxime Ripard authored
The pinctrl groups for SPI until now were also adding the chip selects in the SPI pinctrl group. This was causing a few issues, since a board was forced to use a random number of chipselects, even though it might use one of these chip selects for another pin. The number of chipselects defined was also not the same from one group to another because of different needs at the time these groups have been introduced, resulting in no clear view from the board DTS on what exactly is being muxed, which even might change in the future. Solve this by creating different pinctrl groups for the chipselects and the standard SPI pins (CLK, MOSI and MISO) so that we fix both issues. Signed-off-by: -
Maxime Ripard authored
A few lines (probably copy pasted) have an indentation mixing tabs and spaces that triggers a checkpatch warning. Fix those, and while we're at it, fix the space-indented sections. Signed-off-by: -
Maxime Ripard authored
A few lines in our DTSIs are over the 80 characters limit, making checkpatch complain about that. If possible (and relevant), wrap these lines to 80 characters. Signed-off-by: -
Maxime Ripard authored
The FSF address triggers a warning on checkpatch, saying that the FSF license is already present in the Linux source code, and that it has already changed in the past. Remove it from our DT, as suggested. Signed-off-by:
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- 02 May, 2015 1 commit
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Marcus Cooper authored
Currently none of the target boards nor the driver supports IR TX. However this pin is used in a few instances as a GPIO. Split the pin ctrl descriptions so that only the IR RX is configured to be used. Signed-off-by:
Marcus Cooper <codekipper@gmail.com> Signed-off-by:
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- 29 Apr, 2015 1 commit
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Marcus Cooper authored
The MK808C is an A20 based android stick, with 1G RAM, 8G NAND flash, a RTL8723au wifi + bt combo chip, a USB host ports using USB-A receptacles, a mini USB-B receptacle for USB OTG, mini HDMI and a TRS connector for AV. This patch adds basic support for the device, more information can be found here (http://linux-sunxi.org/MK808C). Signed-off-by:
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- 27 Apr, 2015 18 commits
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Chen-Yu Tsai authored
On sun6i we already have PLL6 as AHB1 clock's parent. However this was previously set in the dma controller node, which takes effect when the dma controller is probed. We want this to take effect as soon as possible, so hrtimer rate calculation is correct, and to be sure the AHB1 clock rate remains as stable as possible. Signed-off-by:
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Chen-Yu Tsai authored
The clock driver now supports a muxable ahb clock. Update the dtsi with the proper compatible and add the new parent clocks. This also adds the new pll6/4 output for pll6 on sun7i-a20. The output is not used on sun4/5i. Also use assigned-clocks to reparent ahb to pll6. We want ahb to have a stable, non-changing clock rate. cpu/axi clock rate changes as a result of newly added cpufreq support. Signed-off-by:
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Hans de Goede authored
The Jesurun Q5 has a black plastic casing with the approximate dimensions of 100mm x 100mm x 24mm with rounded edges. In terms of hardware it features an Allwinner A10 SoC with 1GB RAM and 8GB of NAND flash. The external connectors are: 2x USB-A female supporting USB2.0, 3.5mm female jack for audio, HDMI female, SPDIF, RJ45 LAN and Power. In addition the device has 1x red LED (hard wired to power) and an programmable green led. On the board there is also an unpopulated IR receiver and the UART. The devices is equipped with an AXP209 PMU. For more details see: http://linux-sunxi.org/Jesurun_Q5Signed-off-by:
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Hans de Goede authored
Add a node for the chipone-icn8318 touchscreen found on the Utoo P66 tablet. Signed-off-by:
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Hans de Goede authored
The Orangepi mini is a development board using the Allwinner A20 SoC, with 1G RAM, 2 microsd slots (use the top side one for booting), HDMI, 1Gbit ethernet, USB wifi, Micro USB (otg), sata, 4 USB A ports, ir receiver and a headphones jack. Also see: http://linux-sunxi.org/Xunlong_Orange_Pi_Mini http://www.orangepi.org/Signed-off-by:
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Hans de Goede authored
The Orangepi is a development board using the Allwinner A20 SoC, with 1G RAM, microsd slot, HDMI, 1Gbit ethernet, USB wifi, Micro USB (otg), sata, 4 USB A ports, ir receiver and a headphones jack. Also see: http://linux-sunxi.org/Xunlong_Orange_Pi http://www.orangepi.org/Signed-off-by:
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Maxime Ripard authored
The A20 has a few SRAM that can be mapped either to a device or to the CPU, with the mapping being controlled by a SRAM controller. Since most of the time these SRAM won't be accessible by the CPU, we can't use the mmio-sram driver and compatible. Signed-off-by:
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Hans de Goede authored
The A13 / A10s has a few SRAM that can be mapped either to a device or to the CPU, with the mapping being controlled by a SRAM controller. Since most of the time these SRAM won't be accessible by the CPU, we can't use the mmio-sram driver and compatible. Signed-off-by:
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Hans de Goede authored
The A10 has a few SRAM that can be mapped either to a device or to the CPU, with the mapping being controlled by a SRAM controller. Since most of the time these SRAM won't be accessible by the CPU, we can't use the mmio-sram driver and compatible. Signed-off-by:
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Hans de Goede authored
The eMMC on the A13 based Utoo-P66 tablet does not properly support hpi, and trying to enable it results in the eMMC not working, so add a child-node describing the eMMC, and set the broken-hpi property on it. Signed-off-by:
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Chen-Yu Tsai authored
Add enable-method property to enable SMP support. Signed-off-by:
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Chen-Yu Tsai authored
The core temperature sensor now supports thermal zones. Add a thermal zone mapping for the cpus with passive cooling (cpufreq throttling). Signed-off-by:
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Chen-Yu Tsai authored
The cpu core is clocked from the "cpu" clock. Add a reference to it in the first cpu node. Also add "cpu0" label to the node. The operating points were taken from the a list compiled by Maxime Ripard, which is based on A31 FEX files from the sunxi-boards repository. Not all boards have the same settings. The settings in this patch are the ones shared by A/B/C revisions, plus the default clock setting from u-boot. Signed-off-by:
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Maxime Ripard authored
Add UART aliases and stdout-path property for all the Allwinner boards so that we won't have to rely on the bootargs' console= value, while working with legacy bootloaders. While we're at it, also remove the mentions of earlyprintk in the bootargs, that will remove our default bootargs entirely, and allow the kernel to boot on a system even if DEBUG_LL is configured for another system. Signed-off-by: -
Hans de Goede authored
Remove the unused usb1_vbus_pin_csq908 node (vbus is always on on the cs908), and sort the remaining nodes alphabetically. Signed-off-by:
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Chen-Yu Tsai authored
Since the phy core already supports specifying a regulator to handle during power up/down, it was decided to drop the regulator support in the sun9i usb phy driver. This patch switches the DT to the core bindings. This and the phy driver would be in the same release and should not be a problem as far as DT stability goes. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
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Chen-Yu Tsai authored
The A80 SoC has the architected timer, but the existing firmware from Allwinner does not set CNTFRQ at all. Signed-off-by:
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Chen-Yu Tsai authored
The A23 SoC has the architected timer, but the existing firmware from Allwinner does not set CNTFRQ at all. Signed-off-by:
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