- 30 Aug, 2017 40 commits
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Masahiro Yamada authored
This commit provides similar cleanups as commit 83eacdfa ("mmc: sdhci: disable the clock in sdhci_pltfm_unregister()") did for unregister hooks. sdhci-brcmstb.c and sdhci-sirf.c implement their own suspend/resume hooks to handle pltfm_host->clk. Move clock handling to sdhci_pltfm.c so that the drivers can reuse sdhci_pltfm_pmops. The following drivers did not previously touch pltfm_host->clk during suspend/resume, but now do: - sdhci-bcm-kona.c - sdhci-dove.c - sdhci-iproc.c - sdhci-pxav2.c - sdhci-tegra.c - sdhci-xenon.c Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Acked-by:
Al Cooper <alcooperx@gmail.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Masahiro Yamada authored
The difference between sdhci_pxav2_remove() and sdhci_pltfm_unregister() is clk_put(). It will go away by using the managed resource clk, then sdhci_pltfm_unregister() can be reused. Also, rename the jump labels to say what the goto does. (Coding style suggested by Documentation/process/coding-style.rst) Signed-off-by:
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Masahiro Yamada authored
Currently, the probe function initializes the PHY, but PHY settings are lost during the sleep state. Restore the PHY registers when resuming. To facilitate this, split sdhci_cdns_phy_init() into the DT parse part and PHY update part so that the latter can be invoked from the resume hook. Signed-off-by:
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Hu Ziji authored
Support HS400 Enhanced Strobe feature in Xenon. Enable Enhanced Strobe together with Data Strobe. Disable Enhanced Strobe when eMMC is not in HS400 mode. Signed-off-by:
Hu Ziji <huziji@marvell.com> Signed-off-by:
Zhoujie Wu <zjwu@marvell.com> Acked-by:
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Kishon Vijay Abraham I authored
TI's implementation of sdhci controller used in DRA7 SoC's has CRC in responses with length 136 bits. Add quirk to indicate the controller has CRC in MMC_RSP_136. If this quirk is set sdhci library shouldn't shift the response present in SDHCI_RESPONSE register. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Acked-by:
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Adrian Hunter authored
Read each register only once and move the code to a separate function so that it is not jammed against the 80 column margin. Signed-off-by:
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Jerome Brunet authored
Remove unused clock rate defines. These should not be defined but requested from the clock framework. Also correct typo on the DELAY register Reviewed-by:
Kevin Hilman <khilman@baylibre.com> Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com> Signed-off-by:
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Jerome Brunet authored
Remove CLK_DIVIDER_ALLOW_ZERO. This flag means that a 1 based divider with a 0 value will behave as a bypass clock The mmc divider does not behave like this, a 0 value disables the clock Remove this flag so CCF never allows a 0 value on this clock Fixes: 51c5d844 ("MMC: meson: initial support for GX platforms") Reviewed-by:
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Jerome Brunet authored
CCF generic mux will shift the mask using the value defined in shift Define the mask accordingly Reviewed-by:
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Linus Walleij authored
Instead of passing a block device to mmc_blk_ioctl[_multi]_cmd(), let's pass struct mmc_blk_data() so we operate ioctl()s on the MMC block device representation rather than the vanilla block device. This saves a little duplicated code and makes it possible to issue ioctl()s not targeted for a specific block device but rather for a specific partition/area. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Linus Walleij authored
Instead of passing a struct mmc_blk_data * to mmc_blk_part_switch() let's pass the actual partition type we want to switch to. This is necessary in order not to have a block device with a backing mmc_blk_data and request queue and all for every hardware partition, such as RPMB. Signed-off-by:
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Linus Walleij authored
mmc_blk_ioctl() calls either mmc_blk_ioctl_cmd() or mmc_blk_ioctl_multi_cmd() and each of these make the same check. Factor it into a new helper function, call it on both branches of the switch() statement and save a chunk of duplicate code. Cc: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by:
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Linus Walleij authored
If we don't have the block layer enabled, we do not present card status and extcsd in the debugfs. Debugfs is not ABI, and maintaining files of no relevance for non-block devices comes at a high maintenance cost if we shall support it with the block layer compiled out. The debugfs entries suffer from all the same starvation issues as the other userspace things, under e.g. a heavy dd operation. The expected number of debugfs users utilizing these two debugfs files is already low as there is an ioctl() to get the same information using the mmc-tools, and of these few users the expected number of people using it on SDIO or combo cards are expected to be zero. It is therefore logical to move this over to the block layer when it is enabled, using the new custom requests and issue it using the block request queue. On the other hand it moves some debugfs code from debugfs.c and into block.c. Tested during heavy dd load by cat:in the status file. Signed-off-by:
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Linus Walleij authored
This function retrieves the status of the card with the default number of retries. Since the block layer wants to use this, and since the block layer is a loadable kernel module, we need to export this symbol. Signed-off-by:
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Linus Walleij authored
We have a data pointer for the ioctl() data, but we need to pass other data along with the DRV_OP:s, so make this a void * so it can be reused. Signed-off-by:
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Axel Lin authored
Get rid of boilerplate code by using module_platform_driver macro. Signed-off-by:
Axel Lin <axel.lin@ingics.com> Acked-by:
Jan Glauber <jglauber@cavium.com> Signed-off-by:
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Fabrizio Castro authored
Signed-off-by:
Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by:
Chris Paterson <chris.paterson2@renesas.com> Acked-by:
Simon Horman <horms+renesas@verge.net.au> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Arnd Bergmann authored
The new lockdep annotations for completions cause a warning in the mmc test module, in a function that now has four 150 byte structures on the stack: drivers/mmc/core/mmc_test.c: In function 'mmc_test_nonblock_transfer.constprop': drivers/mmc/core/mmc_test.c:892:1: error: the frame size of 1360 bytes is larger than 1024 bytes [-Werror=frame-larger-than=] The mmc_test_ongoing_transfer function evidently had a similar problem, and worked around it by using dynamic allocation. This generalizes the approach used by mmc_test_ongoing_transfer() and applies it to mmc_test_nonblock_transfer() as well. Fixes: cd8084f9 ("locking/lockdep: Apply crossrelease to completions") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Acked-by:
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yangbo lu authored
eSDHC is not a standard SD host controller. SDHCI_CAPABILITIES_1 register address is 0x44 while it's 0x114 (ESDHC_CAPABILITIES_1) for eSDHC. Signed-off-by:
Yangbo Lu <yangbo.lu@nxp.com> Acked-by:
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yangbo lu authored
SD controller with SDHCI_QUIRK_NO_HISPD_BIT quirk probably use high speed enable bit for other purpose. So this bit shouldn't be changed for high speed enabling for this type of SD controller. Signed-off-by:
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Michał Mirosław authored
Now that sdhci_set_bus_width() supports 8-bit bus widths based on the MMC_CAP_8_BIT_DATA capability flag, replace the sdhci-s3c version with the generic sdhci version. Signed-off-by:
Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by:
Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by:
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Michał Mirosław authored
Now that sdhci_set_bus_width() supports 8-bit bus widths based on the MMC_CAP_8_BIT_DATA capability flag, replace the sdhci-pci version with the generic sdhci version. Signed-off-by:
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Michał Mirosław authored
Now that sdhci_set_bus_width() supports 8-bit bus widths based on the MMC_CAP_8_BIT_DATA capability flag, replace the tegra version with the generic sdhci version. Signed-off-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
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Michał Mirosław authored
Hosts supporting 8-bit bus are marked accordingly. If MMC_CAP_8_BIT_DATA is not among host capabilities, 8BITBUS bit will never be set and it is not cleared in case some non-SDHCI3 host uses it for something else. Signed-off-by:
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Biju Das authored
Add support for r8a7743/5 SoC. Renesas RZ/G1[ME] (R8A7743/5) SDHI is identical to the R-Car Gen2 family. Signed-off-by:
Biju Das <biju.das@bp.renesas.com> Reviewed-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by:
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Adrian Hunter authored
CQE needs to be off for the host controller to accept non-CQ commands. Turn off the CQE before sending commands, and ensure it is off in any reset or power management paths, or re-tuning. Signed-off-by:
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Adrian Hunter authored
Add CQE host operations, capabilities, and host members. Signed-off-by:
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Adrian Hunter authored
Most of the information needed to issue requests to a CQE is already in struct mmc_request and struct mmc_data. Add data block address, some flags, and the task id (tag), and allow for cmd being NULL which it is for CQE tasks. Signed-off-by:
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Adrian Hunter authored
mmc_return_hold() / mmc_retune_release() are used around a group of commands to prevent re-tuning between the commands. Re-tuning can still happen before the first command. In some cases, re-tuning must be prevented entirely. Add mmc_retune_hold_now() for that purpose. It is added in preparation for CQE support where it will be used by CQE recovery. Signed-off-by:
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Adrian Hunter authored
Packed commands support was removed but some bits got left behind. Remove them. Signed-off-by:
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Chen-Yu Tsai authored
sunxi_mmc_clk_set_phase expects the actual card clock rate to be passed to it. When the internal divider code was reworked in change ("mmc: sunxi: Support MMC DDR52 transfer mode with new timing mode"), this requirement was missed, and the module clock rate was passed in instead. This broke 8 bit DDR MMC on old controllers, as the module clock rate is double the card clock rate, for which we have no valid delay settings. Fix this by applying the internal divider to the clock rate right after we configure it in hardware. Signed-off-by:Chen-Yu Tsai <wens@csie.org> Signed-off-by:
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Wolfram Sang authored
Make use of the 64 bit sdbuf width on Renesas R-Car Gen3. If the registers are 8 byte apart, the width is also 64 bit. For all others, the width is 32 bit, even if the registers are only 16 bit apart. Signed-off-by:
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Wolfram Sang authored
We don't use this new define yet, but it is helpful to document which versions we know of. Signed-off-by:
Chris Brandt <Chris.Brandt@renesas.com> Reviewed-by:
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Wolfram Sang authored
It is documented, so enable it to follow the recommendation in the docs and also save a few cycles. Signed-off-by:
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Wolfram Sang authored
There is one SDHI instance on Gen2 which does not have the CBSY bit. So, turn CBSY usage into an extra flag and set it accordingly. This has the additional advantage that we can also set it for other incarnations later. Signed-off-by:
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Arvind Yadav authored
usb_device_id are not supposed to change at runtime. All functions working with usb_device_id provided by <linux/usb.h> work with const usb_device_id. So mark the non-const structs as const. Signed-off-by:
Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by:
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Hu Ziji authored
Add Xenon specific system-level suspend and resume support. Especially during resume, re-configure Xenon specific registers since registers setting will be lost in suspend if Xenon is power off. Signed-off-by:
Jisheng Zhang <jszhang@marvell.com> Acked-by:
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Addy Ke authored
Per the databook of designware mmc controller 2.70a, table 3-2, cmd done interrupt should be fired as soon as the the cmd is sent via cmd line. And the response timeout interrupt should be generated unconditioinally as well if the controller doesn't receive the resp. However that doesn't seem to meet the fact of rockchip specified Soc platforms using dwmmc. We have continuously found the the cmd done or response timeout interrupt missed somehow which took us a long time to understand what was happening. Finally we narrow down the root to the reconstruction of sample circuit for dwmmc IP introduced by rockchip and the buggy design sweeps over all the existing rockchip Socs using dwmmc disastrously. It seems no way to work around this bug without the proper break-out mechanism so that we seek for a parallel pair the same as the handling for missing data response timeout, namely dto timer. Adding this cto timer seems easily to handle this bug but it's hard to restrict the code under the rockchip specified context. So after merging this patch, it sets up the cto timer for all the platforms using dwmmc IP which isn't ideal but at least we don't advertise new quirk here. Fortunately, no obvious performance regression was found by test and the pre-existing similar catch-all timer for sdhci has proved it's an acceptant way to make the code as robust as possible. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=196321Signed-off-by:
Addy Ke <addy.ke@rock-chips.com> Signed-off-by:
Ziyuan Xu <xzy.xu@rock-chips.com> [shawn.lin: rewrite the code and the commit msg throughout] Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by:
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liwei authored
Add sd card support for hi3660 soc Signed-off-by:
Li Wei <liwei213@huawei.com> Signed-off-by:
Chen Jun <chenjun14@huawei.com> Signed-off-by:
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liwei authored
This commit modifies dw_mci_probe(), it moves reset assertion before drv_data->init(host) Some driver needs to access controller registers in its .init() ops. So, in order to make such access safe, we should do controller reset before .init() being called. Signed-off-by:
Guodong Xu <guodong.xu@linaro.org> Signed-off-by:
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