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- 19 Feb, 2016 1 commit
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Thomas Petazzoni authored
This commits adds a new irqchip driver that handles the ODMI controller found on Marvell 7K/8K processors. The ODMI controller provide MSI interrupt functionality to on-board peripherals, much like the GIC-v2m. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1455888883-5127-1-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: Jason Cooper <jason@lakedaemon.net>
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- 18 Feb, 2016 1 commit
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Mans Rullgard authored
This adds support for the secondary interrupt controller used in Sigma Designs SMP86xx and SMP87xx chips. Signed-off-by: Mans Rullgard <mans@mansr.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1453313237-18570-2-git-send-email-mans@mansr.comSigned-off-by: Jason Cooper <jason@lakedaemon.net>
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- 17 Feb, 2016 2 commits
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Alban Bedel authored
Signed-off-by: Alban Bedel <albeu@free.fr> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1453553867-27003-2-git-send-email-albeu@free.frSigned-off-by: Jason Cooper <jason@lakedaemon.net>
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Alban Bedel authored
The driver stays the same but the initialization changes a bit. For OF boards we now get the memory map from the OF node and use a linear mapping instead of the legacy mapping. For legacy boards we still use a legacy mapping and just pass down all the parameters from the board init code. Signed-off-by: Alban Bedel <albeu@free.fr> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1453553867-27003-1-git-send-email-albeu@free.frSigned-off-by: Jason Cooper <jason@lakedaemon.net>
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- 16 Feb, 2016 1 commit
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Thomas Petazzoni authored
Instead of building the irq-armada-370-xp driver directly when CONFIG_ARCH_MVEBU is enabled, this commit introduces an intermediate CONFIG_ARMADA_370_XP_IRQ hidden Kconfig option. This allows this option to select other interrupt-related Kconfig options (which will be needed in follow-up commits) rather than having such selects done from arch/arm/mach-<foo>/. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1455115621-22846-2-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: Jason Cooper <jason@lakedaemon.net>
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- 24 Jan, 2016 1 commit
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Cristian Birsan authored
This adds support for the interrupt controller present on PIC32 class devices. It handles all internal and external interrupts. This controller exists outside of the CPU core and is the arbitrator of all interrupts (including interrupts from the CPU itself) before they are presented to the CPU. The following features are supported: - DT properties for EVIC and for devices/peripherals that use interrupt lines - Persistent and non-persistent interrupt handling - irqdomain and generic chip support - Configuration of external interrupt edge polarity Signed-off-by: Cristian Birsan <cristian.birsan@microchip.com> Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12092/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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- 29 Dec, 2015 1 commit
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Damien Riegel authored
This commit adds support for the TS-4800 interrupt controller. This controller is instantiated in a companion FPGA, and multiplex interrupts for other FPGA IPs. As this component is external to the SoC, the SoC might need to reserve pins, so this controller is implemented as a platform driver and doesn't use the IRQCHIP_DECLARE construct. Signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: kernel@savoirfairelinux.com Link: http://lkml.kernel.org/r/1450728683-31416-2-git-send-email-damien.riegel@savoirfairelinux.comSigned-off-by: Thomas Gleixner <tglx@linutronix.de>
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- 18 Dec, 2015 1 commit
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Ma Jun authored
Mbigen means Message Based Interrupt Generator(MBIGEN). Its a kind of interrupt controller that collects the interrupts from external devices and generate msi interrupt. Mbigen is applied to reduce the number of wire connected interrupts. As the peripherals increasing, the interrupts lines needed is increasing much, especially on the Arm64 server SOC. Therefore, the interrupt pin in GIC is not enough to cover so many peripherals. Mbigen is designed to fix this problem. Mbigen chip locates in ITS or outside of ITS. Mbigen chip hardware structure shows as below: mbigen chip |---------------------|-------------------| mgn_node0 mgn_node1 mgn_node2 | |-------| |-------|------| dev1 dev1 dev2 dev1 dev3 dev4 Each mbigen chip contains several mbigen nodes. External devices can connect to mbigen node through wire connecting way. Because a mbigen node only can support 128 interrupt maximum, depends on the interrupt lines number of devices, a device can connects to one more mbigen nodes. Also, several different devices can connect to a same mbigen node. When devices triggered interrupt,mbigen chip detects and collects the interrupts and generates the MBI interrupts by writing the ITS Translator register. To simplify mbigen driver,I used a new conception--mbigen device. Each mbigen device is initialized as a platform device. Mbigen device presents the parts(register, pin definition etc.) in mbigen chip corresponding to a peripheral device. So from software view, the structure likes below mbigen chip |---------------------|-----------------| mbigen device1 mbigen device2 mbigen device3 | | | dev1 dev2 dev3 Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Ma Jun <majun258@huawei.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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- 16 Dec, 2015 1 commit
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Linus Walleij authored
The ARM RealView PB11MPCore reference design has some special bits in a system controller register to set up the GIC in one of three modes: legacy, new with DCC, new without DCC. The register is also used to enable FIQ. Since the platform will not boot unless this register is set up to "new with DCC" mode, we need a special quirk to be compiled-in for the RealView platforms. If we find the right compatible string on the GIC TestChip, we enable this quirk by looking up the system controller and enabling the special bits. We depend on the CONFIG_REALVIEW_DT Kconfig symbol as the old boardfile code has the same fix hardcoded, and this is only needed for the attempts to modernize the RealView code using device tree. After fixing this, the PB11MPCore boots with device tree only. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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- 14 Oct, 2015 1 commit
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Oleksij Rempel authored
Freescale iMX23/iMX28 and Alphascale ASM9260 have similar interrupt collectors. We already prepared the mxs driver to handle a different register layout. Add the actual ASM9260 support. Differences between these devices: - Different register offsets - Different count of interupt lines per register - ASM9260 does not provide reset bit - ASM9260 does not support FIQ. Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Tested-by: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: marc.zyngier@arm.com Cc: jason@lakedaemon.net Link: http://lkml.kernel.org/r/1444677334-12242-6-git-send-email-linux@rempel-privat.deSigned-off-by: Thomas Gleixner <tglx@linutronix.de>
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- 24 Aug, 2015 1 commit
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Shenwei Wang authored
IMX7D contains a new version of GPC IP block (GPCv2). It has two major functions: power management and wakeup source management. When the system is in WFI (wait for interrupt) mode, the GPC block will be the first block on the platform to be activated and signaled. In normal wait mode during cpu idle, the system can be woken up by any enabled interrupts. In standby or suspend mode, the system can only be wokem up by the pre-defined wakeup sources. Based-on-patch-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shenwei Wang <shenwei.wang@freescale.com> Cc: <linux-arm-kernel@lists.infradead.org> Cc: <shawn.guo@linaro.org> Cc: <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/1440443055-7291-1-git-send-email-shenwei.wang@freescale.comSigned-off-by: Thomas Gleixner <tglx@linutronix.de>
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- 20 Aug, 2015 1 commit
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Eric Anholt authored
This interrupt controller is the new root interrupt controller with the timer, PMU events, and IPIs, and the bcm2835's interrupt controller is chained off of it to handle the peripherals. I wrote the interrupt chip support, while Andrea Merello wrote the IPI code. Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Cc: linux-rpi-kernel@lists.infradead.org Cc: Lee Jones <lee@kernel.org> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/1438902033-31477-5-git-send-email-eric@anholt.netSigned-off-by: Thomas Gleixner <tglx@linutronix.de>
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- 31 Jul, 2015 1 commit
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Ralf Baechle authored
Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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- 29 Jul, 2015 2 commits
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Marc Zyngier authored
In order to support non-PCI MSI with the GICv3 ITS, add the minimal required entry points for the MSI domain (an msi_prepare implementation). The rest is only boilerplate code to find the raw ITS domain. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Cc: <linux-arm-kernel@lists.infradead.org> Cc: Yijing Wang <wangyijing@huawei.com> Cc: Ma Jun <majun258@huawei.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Duc Dang <dhdang@apm.com> Cc: Hanjun Guo <hanjun.guo@linaro.org> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: Jason Cooper <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/1438091186-10244-16-git-send-email-marc.zyngier@arm.comSigned-off-by: Thomas Gleixner <tglx@linutronix.de>
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Marc Zyngier authored
It is becoming obvious that having the PCI/MSI code in the same file as the the core ITS code is giving people implementing non-PCI MSI support the wrong kind of idea. In order to make things a bit clearer, let's move the PCI/MSI code out to its own file. Hopefully it will make it clear that whoever thinks of hooking into the core ITS better have a very strong point. We use a temporary entry point that will get removed in a subsequent patch, once the proper infrastructure is added. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Cc: <linux-arm-kernel@lists.infradead.org> Cc: Yijing Wang <wangyijing@huawei.com> Cc: Ma Jun <majun258@huawei.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Duc Dang <dhdang@apm.com> Cc: Hanjun Guo <hanjun.guo@linaro.org> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: Jason Cooper <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/1438091186-10244-12-git-send-email-marc.zyngier@arm.comSigned-off-by: Thomas Gleixner <tglx@linutronix.de>
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- 23 Jun, 2015 1 commit
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Yoshinori Sato authored
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
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- 21 Jun, 2015 2 commits
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Paul Burton authored
Move the driver for Ingenic SoC interrupt controllers into drivers/irqchip where it belongs. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Brian Norris <computersforpeace@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/10147/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
While at it, rename it because in drivers/irqchip no longer every CPU is a MIPS. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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- 28 May, 2015 1 commit
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Dmitry Eremin-Solenikov authored
Move current sa11x0 IRQ driver to the irqchip subsystem. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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- 01 Apr, 2015 1 commit
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Kevin Cernekee authored
This is the main peripheral IRQ controller on the BCM7xxx MIPS chips; it has the following characteristics: - 64 to 160+ level IRQs - Atomic set/clear registers - Reasonably predictable register layout (N status words, then N mask status words, then N mask set words, then N mask clear words) - SMP affinity supported on most systems - Typically connected to MIPS IRQ 2,3,2,3 on CPUs 0,1,2,3 This driver registers one IRQ domain and one IRQ chip to cover all instances of the block. Up to 4 instances of the block may appear, as it supports 4-way IRQ affinity on BCM7435. The same block exists on the ARM BCM7xxx chips, but typically the ARM GIC is used instead. So this driver is primarily intended for MIPS STB chips. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8844/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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- 15 Mar, 2015 1 commit
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Marc Zyngier authored
Tegra's LIC (Legacy Interrupt Controller) has been so far only supported as a weird extension of the GIC, which is not exactly pretty. The stacked IRQ domain framework fits this pretty well, and allows the LIC code to be turned into a standalone irqchip. In the process, make the driver DT aware, something that was sorely missing from the mach-tegra implementation. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1426088583-15097-3-git-send-email-marc.zyngier@arm.comSigned-off-by: Jason Cooper <jason@lakedaemon.net>
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- 08 Mar, 2015 1 commit
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Stefan Agner authored
This adds support for Vybrid's interrupt router. On VF6xx models, almost all peripherals can be used by either of the two CPU's, the Cortex-A5 or the Cortex-M4. The interrupt router routes the peripheral interrupts to the configured CPU. This IRQ chip driver configures the interrupt router to route the requested interrupt to the CPU the kernel is running on. The driver makes use of the irqdomain hierarchy support. The parent is given by the device tree. This should be one of the two possible parents either ARM GIC or the ARM NVIC interrupt controller. The latter is currently not yet supported. Note that there is no resource control mechnism implemented to avoid concurrent access of the same peripheral. The user needs to make sure to use device trees which assign the peripherals orthogonally. However, this driver warns the user in case the interrupt is already configured for the other CPU. This provides a poor man's resource controller. Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Link: https://lkml.kernel.org/r/1425249689-32354-2-git-send-email-stefan@agner.chSigned-off-by: Jason Cooper <jason@lakedaemon.net>
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- 03 Mar, 2015 1 commit
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Lee Jones authored
This driver is used to enable System Configuration Register controlled External, CTI (Core Sight), PMU (Performance Management), and PL310 L2 Cache IRQs prior to use. Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lkml.kernel.org/r/1424272444-16230-3-git-send-email-lee.jones@linaro.orgSigned-off-by: Jason Cooper <jason@lakedaemon.net>
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- 26 Jan, 2015 1 commit
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Baruch Siach authored
Add interrupt controller driver to the Conexant CX92755 SoC, part of the Digicolor SoCs series. Use the generic irq framework support. Use syscon to access the system global UC_IRQ_CONTROL register. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Cc: linux-arm-kernel@lists.infradead.org Cc: Arnd Bergmann <arnd@arndb.de> Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/5b769e3c23dfa5fde08c4f3bc966c2c2b3921d8a.1421317616.git.baruch@tkos.co.ilSigned-off-by: Thomas Gleixner <tglx@linutronix.de>
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- 26 Nov, 2014 3 commits
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Suravee Suthikulpanit authored
ARM GICv2m specification extends GICv2 to support MSI(-X) with a new register frame. This allows a GICv2 based system to support MSI with minimal changes. Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> [maz: converted the driver to use stacked irq domains, updated changelog] Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416941243-7181-2-git-send-email-marc.zyngier@arm.comSigned-off-by: Jason Cooper <jason@lakedaemon.net>
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Yingjoe Chen authored
Mediatek SoCs have interrupt polarity support in sysirq which allows to invert polarity for given interrupt. Add this support using hierarchy irq domain. Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Link: https://lkml.kernel.org/r/1416902662-19281-3-git-send-email-yingjoe.chen@mediatek.comSigned-off-by: Jason Cooper <jason@lakedaemon.net>
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Marc Zyngier authored
Get the show on the road... Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-13-git-send-email-marc.zyngier@arm.comSigned-off-by: Jason Cooper <jason@lakedaemon.net>
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- 24 Nov, 2014 1 commit
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Andrew Bresticker authored
Move GIC irqchip support to drivers/irqchip/ and rename the Kconfig option from IRQ_GIC to MIPS_GIC to avoid confusion with the ARM GIC. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7812/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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- 09 Nov, 2014 1 commit
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Kevin Cernekee authored
Some chips, such as BCM6328, only require bcm7120-l2. Some BCM7xxx STB configurations only require brcmstb-l2. Treat them as two separate entities, and update the mach-bcm dependencies to reflect the change. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lkml.kernel.org/r/1415342669-30640-13-git-send-email-cernekee@gmail.comSigned-off-by: Jason Cooper <jason@lakedaemon.net>
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- 16 Sep, 2014 1 commit
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Felipe Balbi authored
Just move the code over as it has no dependencies on arch/arm/ anymore. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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- 14 Sep, 2014 1 commit
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Florian Fainelli authored
This patch adds support for the Level-2 interrupt controller hardware found in Broadcom Set Top Box System-on-a-Chip devices. This interrupt controller is implemented using a single enable register. This interrupt controller is always present on the platforms supported by the irq-brcmstb-l2 driver, hence the reason why both are compiled using the same Kconfig symbol. [jac] removed the following warning: drivers/irqchip/irq-bcm7120-l2.c: In function 'bcm7120_l2_intc_irq_handle': drivers/irqchip/irq-bcm7120-l2.c:49:27: warning: unused variable 'gc' [-Wunused-variable] Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lkml.kernel.org/r/1410309862-27784-2-git-send-email-f.fainelli@gmail.comSigned-off-by: Jason Cooper <jason@lakedaemon.net>
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- 20 Aug, 2014 1 commit
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Haojian Zhuang authored
HiP04 GIC is the variate of ARM GICv2. ARM GICv2 supports 8 cores. HiP04 GIC extends to support 16 cores. It results that bit fields in GIC_DIST_TARGET & GIC_DIST_SOFTINT are different from ARM GICv2. And the maximium IRQ is downgrade from 1020 to 510. Since different register offset & bitfields definitation breaks compartible with ARM GICv2, create a new hip04 irq driver. And this driver is derived from irq-gic.c to support the Hisilicon HiP04 interrupt controller, which is similar to the GIC, but deviates at some points. Support for power management, non-banked registers, cascaded GICs (and multiple controllers in general) and bigLittle support has been removed from the GIC driver. Affinity related functions have been adjusted to match the Hisilicon hardware implementation. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Link: https://lkml.kernel.org/r/1407408695-19626-9-git-send-email-haojian.zhuang@linaro.orgSigned-off-by: Jason Cooper <jason@lakedaemon.net>
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- 17 Aug, 2014 1 commit
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Grygorii Strashko authored
On Keystone SOCs, DSP cores can send interrupts to ARM host using the IRQ controller IP. It provides 28 IRQ signals to ARM. The IRQ handler running on HOST OS can identify DSP signal source by analyzing SRCCx bits in IPCARx registers. This is one of the component used by the IPC mechanism used on Keystone SOCs. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Link: https://lkml.kernel.org/r/1406126430-9978-1-git-send-email-grygorii.strashko@ti.comSigned-off-by: Jason Cooper <jason@lakedaemon.net>
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- 17 Jul, 2014 1 commit
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Boris BREZILLON authored
Add AIC (Advanced Interrupt Controller) and AIC5 (AIC5 is an evolution of the AIC block) drivers. Put common code in irq-atmel-aic-common.c/.h so that both driver can access shared functions (this will ease maintenance). These drivers are only compatible with dt enabled board and replace the old implementation found in arch/arm/mach-at91/irq.c. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Link: https://lkml.kernel.org/r/1405012462-766-4-git-send-email-boris.brezillon@free-electrons.comSigned-off-by: Jason Cooper <jason@lakedaemon.net>
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- 08 Jul, 2014 2 commits
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Marc Zyngier authored
The Generic Interrupt Controller (version 3) offers services that are similar to GICv2, with a number of additional features: - Affinity routing based on the CPU MPIDR (ARE) - System register for the CPU interfaces (SRE) - Support for more that 8 CPUs - Locality-specific Peripheral Interrupts (LPIs) - Interrupt Translation Services (ITS) This patch adds preliminary support for GICv3 with ARE and SRE, non-secure mode only. It relies on higher exception levels to grant ARE and SRE access. Support for LPI and ITS will be added at a later time. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Zi Shen Lim <zlim@broadcom.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Tirumalesh Chalamarla <tchalamarla@cavium.com> Reviewed-by: Yun Wu <wuyun.wu@huawei.com> Reviewed-by: Zhen Lei <thunder.leizhen@huawei.com> Tested-by: Tirumalesh Chalamarla<tchalamarla@cavium.com> Tested-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Acked-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lkml.kernel.org/r/1404140510-5382-3-git-send-email-marc.zyngier@arm.comSigned-off-by: Jason Cooper <jason@lakedaemon.net>
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Marc Zyngier authored
A few GICv2 low-level function are actually very useful to GICv3, and it makes some sense to share them across the two drivers. They end-up in their own file, with an additional parameter used to ensure an optional synchronization (unused on GICv2). Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1404140510-5382-2-git-send-email-marc.zyngier@arm.comSigned-off-by: Jason Cooper <jason@lakedaemon.net>
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- 01 Jul, 2014 1 commit
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Stefan Kristiansson authored
In addition to consolidating the or1k-pic with other interrupt controllers, this makes OpenRISC less tied to its on-cpu interrupt controller. All or1k-pic specific parts are moved out of irq.c and into drivers/irqchip/irq-or1k-pic.c In that transition, the functionality have been divided into three chip variants. One that handles level triggered interrupts, one that handles edge triggered interrupts and one that handles the interrupt controller that is present in the or1200 OpenRISC cpu implementation. Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> Link: https://lkml.kernel.org/r/1401136302-27654-1-git-send-email-stefan.kristiansson@saunalahti.fiAcked-by: Jonas Bonn <jonas@southpole.se> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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- 27 May, 2014 1 commit
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Florian Fainelli authored
This patch adds support for the Level-2 interrupt controller hardware found in Broadcom Set Top Box System-on-a-Chip devices. This interrupt controller is implemented using the generic IRQ chip driver with separate enable and disable registers. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Link: https://lkml.kernel.org/r/1400892054-24457-2-git-send-email-f.fainelli@gmail.comSigned-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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- 26 Mar, 2014 1 commit
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Carlo Caione authored
Allwinner A20/A31 SoCs have special registers to control / (un)mask / acknowledge NMI. This NMI controller is separated and independent from GIC. This patch adds a new irqchip to manage NMI. Signed-off-by: Carlo Caione <carlo@caione.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-sunxi@googlegroups.com Cc: mark.rutland@arm.com Cc: hdegoede@redhat.com Link: http://lkml.kernel.org/r/1395256879-8475-2-git-send-email-carlo@caione.orgSigned-off-by: Thomas Gleixner <tglx@linutronix.de>
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- 04 Mar, 2014 1 commit
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Jason Cooper authored
This reverts commit 40b367d9. Russell King has raised the idea of creating a proper PMU driver for this SoC that would incorporate the functionality currently in this driver. It would also cover the use case for the graphics subsystem on this SoC. To prevent having to maintain the devicetree ABI for this limited interrupt-handler driver, we revert the driver before it hits a mainline tagged release (eg v3.15). Signed-off-by: Jason Cooper <jason@lakedaemon.net> Cc: linux-arm-kernel@lists.infradead.org Cc: Andrew Lunn <andrew@lunn.ch> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@googlemail.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Russell King - ARM Linux <linux@arm.linux.org.uk> Link: http://lkml.kernel.org/r/1393911160-7688-1-git-send-email-jason@lakedaemon.netSigned-off-by: Thomas Gleixner <tglx@linutronix.de>
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