An error occurred fetching the project authors.
  1. 19 Feb, 2016 1 commit
  2. 18 Feb, 2016 1 commit
  3. 17 Feb, 2016 2 commits
  4. 16 Feb, 2016 1 commit
  5. 24 Jan, 2016 1 commit
  6. 29 Dec, 2015 1 commit
  7. 18 Dec, 2015 1 commit
    • Ma Jun's avatar
      irqchip/mgigen: Add platform device driver for mbigen device · 717c3dbc
      Ma Jun authored
      Mbigen means Message Based Interrupt Generator(MBIGEN).
      
      Its a kind of interrupt controller that collects
      the interrupts from external devices and generate msi interrupt.
      Mbigen is applied to reduce the number of wire connected interrupts.
      
      As the peripherals increasing, the interrupts lines needed is
      increasing much, especially on the Arm64 server SOC.
      
      Therefore, the interrupt pin in GIC is not enough to cover so
      many peripherals.
      
      Mbigen is designed to fix this problem.
      
      Mbigen chip locates in ITS or outside of ITS.
      
      Mbigen chip hardware structure shows as below:
      
      		mbigen chip
      |---------------------|-------------------|
      mgn_node0	  mgn_node1		mgn_node2
       |		 |-------|		|-------|------|
      dev1		dev1    dev2		dev1   dev3   dev4
      
      Each mbigen chip contains several mbigen nodes.
      
      External devices can connect to mbigen node through wire connecting way.
      
      Because a mbigen node only can support 128 interrupt maximum, depends
      on the interrupt lines number of devices, a device can connects to one
      more mbigen nodes.
      
      Also, several different devices can connect to a same mbigen node.
      
      When devices triggered interrupt,mbigen chip detects and collects
      the interrupts and generates the MBI interrupts by writing the ITS
      Translator register.
      
      To simplify mbigen driver,I used a new conception--mbigen device.
      Each mbigen device is initialized as a platform device.
      
      Mbigen device presents the parts(register, pin definition etc.) in
      mbigen chip corresponding to a peripheral device.
      
      So from software view, the structure likes below
      
      	            mbigen chip
           |---------------------|-----------------|
      mbigen device1       mbigen device2  mbigen device3
            |                   |                |
           dev1                dev2             dev3
      Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarMa Jun <majun258@huawei.com>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      717c3dbc
  8. 16 Dec, 2015 1 commit
    • Linus Walleij's avatar
      irqchip/gic: Support RealView variant setup · 8673c1d7
      Linus Walleij authored
      The ARM RealView PB11MPCore reference design has some special
      bits in a system controller register to set up the GIC in one
      of three modes: legacy, new with DCC, new without DCC. The
      register is also used to enable FIQ.
      
      Since the platform will not boot unless this register is set
      up to "new with DCC" mode, we need a special quirk to be
      compiled-in for the RealView platforms.
      
      If we find the right compatible string on the GIC TestChip,
      we enable this quirk by looking up the system controller and
      enabling the special bits.
      
      We depend on the CONFIG_REALVIEW_DT Kconfig symbol as the old
      boardfile code has the same fix hardcoded, and this is only
      needed for the attempts to modernize the RealView code using
      device tree.
      
      After fixing this, the PB11MPCore boots with device tree
      only.
      
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      8673c1d7
  9. 14 Oct, 2015 1 commit
  10. 24 Aug, 2015 1 commit
  11. 20 Aug, 2015 1 commit
  12. 31 Jul, 2015 1 commit
  13. 29 Jul, 2015 2 commits
  14. 23 Jun, 2015 1 commit
  15. 21 Jun, 2015 2 commits
  16. 28 May, 2015 1 commit
  17. 01 Apr, 2015 1 commit
    • Kevin Cernekee's avatar
      IRQCHIP: Add new driver for BCM7038-style level 1 interrupt controllers · 5f7f0317
      Kevin Cernekee authored
      This is the main peripheral IRQ controller on the BCM7xxx MIPS chips;
      it has the following characteristics:
      
       - 64 to 160+ level IRQs
       - Atomic set/clear registers
       - Reasonably predictable register layout (N status words, then N
         mask status words, then N mask set words, then N mask clear words)
       - SMP affinity supported on most systems
       - Typically connected to MIPS IRQ 2,3,2,3 on CPUs 0,1,2,3
      
      This driver registers one IRQ domain and one IRQ chip to cover all
      instances of the block.  Up to 4 instances of the block may appear, as
      it supports 4-way IRQ affinity on BCM7435.
      
      The same block exists on the ARM BCM7xxx chips, but typically the ARM GIC
      is used instead.  So this driver is primarily intended for MIPS STB chips.
      Signed-off-by: default avatarKevin Cernekee <cernekee@gmail.com>
      Cc: f.fainelli@gmail.com
      Cc: jaedon.shin@gmail.com
      Cc: abrestic@chromium.org
      Cc: tglx@linutronix.de
      Cc: jason@lakedaemon.net
      Cc: jogo@openwrt.org
      Cc: arnd@arndb.de
      Cc: computersforpeace@gmail.com
      Cc: linux-mips@linux-mips.org
      Cc: devicetree@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/8844/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      5f7f0317
  18. 15 Mar, 2015 1 commit
  19. 08 Mar, 2015 1 commit
    • Stefan Agner's avatar
      irqchip: vf610-mscm-ir: Add support for Vybrid MSCM interrupt router · 0494e11a
      Stefan Agner authored
      This adds support for Vybrid's interrupt router. On VF6xx models,
      almost all peripherals can be used by either of the two CPU's,
      the Cortex-A5 or the Cortex-M4. The interrupt router routes the
      peripheral interrupts to the configured CPU.
      
      This IRQ chip driver configures the interrupt router to route
      the requested interrupt to the CPU the kernel is running on.
      The driver makes use of the irqdomain hierarchy support. The
      parent is given by the device tree. This should be one of the
      two possible parents either ARM GIC or the ARM NVIC interrupt
      controller. The latter is currently not yet supported.
      
      Note that there is no resource control mechnism implemented to
      avoid concurrent access of the same peripheral. The user needs
      to make sure to use device trees which assign the peripherals
      orthogonally. However, this driver warns the user in case the
      interrupt is already configured for the other CPU. This provides
      a poor man's resource controller.
      Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarStefan Agner <stefan@agner.ch>
      Link: https://lkml.kernel.org/r/1425249689-32354-2-git-send-email-stefan@agner.chSigned-off-by: default avatarJason Cooper <jason@lakedaemon.net>
      0494e11a
  20. 03 Mar, 2015 1 commit
  21. 26 Jan, 2015 1 commit
  22. 26 Nov, 2014 3 commits
  23. 24 Nov, 2014 1 commit
  24. 09 Nov, 2014 1 commit
  25. 16 Sep, 2014 1 commit
  26. 14 Sep, 2014 1 commit
  27. 20 Aug, 2014 1 commit
  28. 17 Aug, 2014 1 commit
  29. 17 Jul, 2014 1 commit
  30. 08 Jul, 2014 2 commits
  31. 01 Jul, 2014 1 commit
  32. 27 May, 2014 1 commit
  33. 26 Mar, 2014 1 commit
  34. 04 Mar, 2014 1 commit