- 07 Dec, 2009 1 commit
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Jeff Garzik authored
This reverts commit f20941f3. Sergei Shtylyov notes "You call min() on uncomparables [in mwdma_clip_to_pio()], i.e. mwdma_to_pio[] contains XFER_PIO_* and adev->pio_mode - XFER_PIO_0 yields you a mode number. Thus the second argument will always "win" as a minimal one" Bartlomiej Zolnierkiewicz adds "There are more issues with the patch related to mwdma_clip_to_pio(). The function can return values between 0 and 4 which obviously won't work well for the new code below for values >2 (i.e. resulting in out-of-bounds array access for the common-case of dev->pio_mode == XFER_PIO_4)." Bartlomiej Zolnierkiewicz also notes the patch is incomplete, failing to update MWDMA mode masks. Signed-off-by:
Jeff Garzik <jgarzik@redhat.com>
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- 03 Dec, 2009 39 commits
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Martin K. Petersen authored
ata_set_lba_range_entries used the variable max for two different things which was confusing. Make the function take a buffer size in bytes as argument and return the used buffer size upon completion. Signed-off-by:
Martin K. Petersen <martin.petersen@oracle.com> Signed-off-by:
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Martin K. Petersen authored
Our current TRIM payload is a single sector that can accommodate 64 * 65535 blocks being unmapped. Report this value in the Block Limits Maximum Unmap LBA count field. If a storage device supports TRIM and the DRAT and RZAT bits are set, report TPRZ=1 in Read Capacity(16). Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
Remove superfluous timings table entry while at it. Signed-off-by:
Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> Acked-by:
Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
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Bartlomiej Zolnierkiewicz authored
MWDMA0 timings cannot be met with the PIIX based controller programming interface. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
Fix register naming while at it. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
Call sis_fixup() on resume. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
Fix ->resume method to re-enable & re-init PCI device properly before doing chipset specific setup. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
Set correct bits to switch between UDMA2 and UDMA4. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
Fix ->resume method to do chipset specific setup. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
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Bartlomiej Zolnierkiewicz authored
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Bartlomiej Zolnierkiewicz authored
We need to mask out the port offset from the port number cached in ld_qdi->timing. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
Dual port QDI6580 has shared PIO timings for master/slave devices so it needs to use custom ->qc_issue method. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
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Bartlomiej Zolnierkiewicz authored
Clear old MWDMA timings before programming new ones (IT8213 is a single port host so there is no need to check ap->port_no). This change should be safe as this is how we have been doing things in IDE it8213 host driver for years. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
[ port of Sergei's fixes for pata_efar from commit 5f33b3bc ] Fix the PIO mode 2 using mode 0 timings -- this driver should enable the fast timing bank starting with PIO2, just like the PIIX/ICH drivers do. Also, fix/rephrase some comments while at it. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
* do not clear PIO timings for master when programming slave * program new PIO timings in the correct register nibble Both changes should be safe as this is how we have been doing things in IDE it8213 host driver for years. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
Driver should program the cycle timing not the mode number (doing the latter results in wrong timings being used). There shouldn't be any problems with it as IDE it8213 host driver has been doing it this way for years. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
Fix ->resume method to re-enable & re-init PCI device properly before doing chipset specific setup. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
It has been dead for the last three years (== since the initial driver merge) and probability that it will ever get fixed is quite low. Since there is no reason to keep this dead code around any longer just remove it (it can still be retrieved from the git history if necessary). Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
Do not clear MWDMA timings for device on the other port when programming slave device. This change should be safe as this is how we have been doing things in IDE slc90e66 host driver for years. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
* do not clear PIO timings for master when programming slave * do not clear PIO timings for device on the other port when programming slave device Both changes should be safe as this is how we have been doing things in IDE slc90e66 host driver for years. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
Fix erroneous check for ap->udma_mask in do_pata_set_dmamode() resulting in controller not being programmed properly for MWDMA. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
This brings struct ata_device in-line with struct ata_{port,host}. Signed-off-by: -
Mark Nelson authored
ahci can drive the Promise PDC42819, but obviously it can only use SATA disks connected to this controller. The controller can actually support SAS disks as well, but we only know how to use it in it's AHCI mode. Add a message to let users know that because ahci is driving their chip they can only use the SATA disks connected to this controller. Signed-off-by:
Mark Nelson <mdnelson8@gmail.com> Signed-off-by:
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Sergei Shtylyov authored
Some places were using PCI_CLASS_REVISION instead of PCI_REVISION_ID, so they weren't converted by commit 44c10138 (PCI: Change all drivers to use pci_device->revision). Signed-off-by:
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Sergei Shtylyov authored
The comment in the driver actually describes HPT37x's timing register layout, which is different from HPT36x. Fix it and reformat the comment, while at it. Bump the driver version, accounting for several patches that forgot to do it. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
Based on: http://lkml.indiana.edu/hypermail/linux/kernel/0908.2/01420.htmlSigned-off-by:
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Sergei Shtylyov authored
These drivers inherited from the older 'hpt366' IDE driver the buggy timing register masks in their set_piomode() metods. As a result, too low command cycle active time is programmed for slow PIO modes. Quite fortunately, it's later "fixed up" by the set_dmamode() methods which also "helpfully" reprogram the command timings, usually to PIO mode 4; unfortunately, setting an UltraDMA mode #N also reprograms already set PIO data timings, usually to MWDMA mode # max(N, 2) timings... However, the drivers added some breakage of their own too: the bit that they set/clear to control the FIFO is sometimes wrong -- it's actually the MSB of the command cycle setup time; also, setting it in DMA mode is wrong as this bit is only for PIO actually and clearing it for PIO modes is not needed as no mode in any timing table has it set... Fix all this, inverting the masks while at it, like in the 'hpt366' and 'pata_hpt366' drivers; bump the drivers' versions, accounting for recent patches that forgot to do it... Signed-off-by:
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Alan Cox authored
We were never able to get docs for this out of Toshiba for years. Dave Barnes produced a NetBSD driver however and from that we can fill in the needed tables. As we correct the PCI identifiers a bit also update the old ide generic driver at the same time so it stays compiling. Signed-off-by:
Alan Cox <alan@linux.intel.com> Signed-off-by:
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Alan Cox authored
Making the new stuff work broke some of the old chipsets. We need to go back to the old set up values for these it seems. Unfortunately even with documentation this is basically a mix of cargoculting and guesswork. Chased down to the exact line by Gianluca. Signed-off-by:
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Alan Cox authored
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Alan Cox authored
Daniela Engert pointed out that there are some implementation notes for the 643 and 646 that deal with certain serialization rules. In theory we don't need them because they apply when the motherboard decides not to retry PCI requests for long enough and the chip is busy doing a DMA transfer on the other channel. The rule basically is "don't touch the taskfile of the other channel while a DMA is in progress". To implement that we need to - not issue a command on a channel when there is a DMA command queued - not issue a DMA command on a channel when there are PIO commands queued - use the alternative access to the interrupt source so that we do not touch altstatus or status on shared IRQ. Updated to remote extra conditional check Bartlomiej noted and to remove the variables for irq checks as the CMD648 doesn't have the underlying problem. Signed-off-by:
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Alan Cox authored
Bartlomiej pointed out that while this got fixed in the old driver whoever did it didn't port it across. Signed-off-by:
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Alan Cox authored
Reported by Mikulas Patocka. VIA VT82C586B + Transcend TS64GSSD25-M v0826 does not work in UDMA mode Signed-off-by:
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Benjamin Herrenschmidt authored
In libata-sff, ata_sff_post_internal_cmd() directly calls ata_bmdma_stop() instead of ap->ops->bmdma_stop(). This can be a problem for controllers that use their own bmdma_stop for which the generic sff one isn't suitable Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
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Christoph Hellwig authored
Add support for the ATA TRIM command in libata. We translate a WRITE SAME 16 command with the unmap bit set into an ATA TRIM command and export enough information in READ CAPACITY 16 and the block limits EVPD page so that the new SCSI layer discard support will driver this for us. Note that I hardcode the WRITE_SAME_16 opcode for now as the patch to introduce the symbolic is not in 2.6.32 yet but only in the SCSI tree - as soon as it is merged we can fix it up to properly use the symbolic name. Signed-off-by:
Christoph Hellwig <hch@lst.de> Signed-off-by:
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Tejun Heo authored
If ATA device failed FLUSH, it means that the device failed to write out some amount of data and the error needs to be reported to upper layers. As retries can't recover the lost data, FLUSH failures need to be reported immediately in general. However, if FLUSH fails due to transmission errors, the FLUSH needs to be retried; otherwise, filesystems may switch to RO mode and/or raid array may drop a drive for a random transmission glitch. This condition can be rather easily reproduced on certain ahci controllers which go through a PHY event after powersave mode switch + ext4 combination. Powersave mode switch is often closely followed by flush from the filesystem failing the FLUSH with ATA bus error which makes the filesystem code believe that data is lost and drop to RO mode. This was reported in the following bugzilla bug. http://bugzilla.kernel.org/show_bug.cgi?id=14543 This patch makes libata EH retry FLUSH if it wasn't failed by the device. Signed-off-by:
Tejun Heo <tj@kernel.org> Reported-by:
Andrey Vihrov <andrey.vihrov@gmail.com> Signed-off-by:
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